AMD today launched three new additions to its 2013 A-Series and E-Series Mobile Accelerated Processing Unit (APU) lineup -- delivering solutions ideally positioned to address today's evolving PC market with dramatically increased performance and power efficiency, as well as a portfolio of unique user experiences, and superior gaming and graphics:

• The 2013 AMD Elite Mobility APU (formerly codenamed "Temash") -- the world's first 28nm, quad-core x86 system-on-a-chip (SoC) APU designed for touch small form-factor notebooks, tablets, and hybrids 13-inches and below;
  
• The 2013 AMD Mainstream APU (formerly codenamed "Kabini") -- the first and only quad-core x86 SoC solution for entry-level and small-form factor touch notebooks;
  
• New, low power versions of the 2013 AMD Elite Performance APU (formerly codenamed "Richland") -- offer the best graphics and compute in a performance APU for premium ultrathin notebooks.
  

Intel Corporation today took the wraps off its brand new, low-power, high-performance microarchitecture named Silvermont. The technology is aimed squarely at low-power requirements in market segments from smartphones to the data center. Silvermont will be the foundation for a range of innovative products beginning to come to market later this year, and will also be manufactured using the company's leading-edge, 22nm Tri-Gate SoC manufacturing process, which brings significant performance increases and improved energy efficiency.

"Silvermont is a leap forward and an entirely new technology foundation for the future that will address a broad range of products and market segments," said Dadi Perlmutter, Intel executive vice president and chief product officer. "Early sampling of our 22nm SoCs, including "Bay Trail" and "Avoton" is already garnering positive feedback from our customers. Going forward, we will accelerate future generations of this low-power microarchitecture on a yearly cadence."

AMD announced today a strategic focus on developing one-of-a-kind solutions through its Semi-Custom Business Unit based on the extensive set of intellectual property (IP) amassed across AMD processors, graphics and multimedia. Providing to customers a level of flexibility and differentiation that goes beyond standard AMD products, the business unit takes AMD to a new level of customer-centric design by integrating these building blocks with customer-specific IP to create tailor-made solutions using a flexible System-on-a-Chip (SoC) design methodology.

AMD's high-performance SoC processor design methodology provides a modular approach, leveraging best practices to readily re-use silicon IP and design building blocks. With the Semi-Custom Business Unit, AMD collaborates with customers to create customized chip solutions that help enable customers to push the boundaries in product development. The business unit features a strong team of engineers who are well-versed in graphics and compute processing, and is led by Corporate Vice President and General Manager Saeid Moshkelani. Moshkelani joined AMD last year from Trident Microsystems and reports to AMD Senior Vice President and General Manager of Global Business Units Lisa Su.

AMD today announced that Raja Koduri, 44, has rejoined the company as corporate vice president, Visual Computing, reporting to Mark Papermaster, senior vice president and chief technology officer. In his new role, Koduri will have overall responsibility for driving AMD's innovation in visual and accelerated computing.

"Maintaining AMD's position as a leader in visual computing is the key to our long-term success. As one of the industry's foremost experts in developing leading-edge visual computing solutions, Raja brings exceptional vision and strength to AMD's world-class engineering leadership team," said Papermaster. "Given his past record of success, Raja will help AMD lead the way in visual and accelerated computing and ensure we continue developing the industry-leading graphics IP that forms the foundation for our future growth."

During her keynote at the Intel Developer Forum today in Beijing, Diane Bryant, senior vice president and general manager of Intel's Datacenter and Connected Systems Group, discussed how her company is helping users harness powerful new capabilities that will improve the lives of people by building smarter cities, healthier communities and thriving businesses.

Bryant unveiled details of upcoming technologies and products that show how Intel aims to transform the server, networking and storage capabilities of the datacenter. By addressing the full spectrum of workload demands and providing new levels of application optimized solutions for enterprise IT, technical computing and cloud service providers, unprecedented experiences can be delivered.

Cadence Design Systems, Inc., today announced an ongoing multi-year agreement with TSMC to develop the design infrastructure for 16-nanometer FinFET technology, targeting advanced node designs for mobile, networking, servers and FPGA applications. The deep collaboration, beginning earlier in the design process than usual, will effectively address the design challenges specific to FinFETs -- from design analysis through signoff -- and will deliver the infrastructure necessary to enable ultra low-power, high-performance chips.

FinFETs help deliver the power, performance, and area (PPA) advantages that are needed to develop highly differentiated SoC designs at 16 nanometers and smaller process technologies. Unlike a planar FET, the FinFET employs a vertical fin-like structure protruding from the substrate with the gate wrapping around the sides and top of the fin, thereby producing transistors with low leakage currents and fast switching performance. This extended Cadence-TSMC collaboration will produce the design infrastructure that chip designers need for accurate electrical characteristics and parasitic models required for advanced FinFET designs for mobile and enterprise applications.

FinalWire announced AIDA64 v2.85, the popular system diagnostic and benchmarking suite is updated with 64-bit benchmarks optimized for AMD's "Richland" APUs, improved support for "Kaveri," "Kabini," and "Temash" APUs; and Intel "Haswell" and "Valleyview" CPUs; early support for AMD "Beema" APU, Intel "Avoton" SoC, "Crystalwell," "Ivy Bridge-E," and "Haswell-E" CPU, "Haswell-ULT" SoC; preliminary support for DDR4 and GDDR5 system memory types; and GPU support for AMD Radeon HD 8000 series and NVIDIA GeForce GTX Titan.DOWNLOAD: FinalWire AIDA64 v2.85 Installer (EXE), Archive (ZIP)

Tensilica, Inc. today announced that it has joined the HSA (Heterogeneous System Architecture) Foundation, a not-for-profit consortium dedicated to developing architecture specifications that will unlock the performance and power efficiency of parallel computing engines found in many modern devices. Tensilica will contribute its years of experience assisting customers in bringing heterogeneous multicore SoC (system-on-chip) designs to market to the development and promotion of standards for parallel computing.

"Tensilica is a long-established leader in multicore technology, delivering unique solutions that enable both control plane and compute-intensive dataplane functions," stated Steve Roddy, Tensilica's vice president of product marketing and business development. "Tensilica customers today use multiple Tensilica processors for diverse functions such as audio offload, wireless baseband, image processing and general purpose control. We welcome the efforts and ambitions of the HSA to bring standards to the market that will greatly facilitate innovation in embedded applications."

Asustor displayed its first consumer NAS devices implementing Intel's recently announced Atom CE5315 SoC. The new model fill into the company's 3-series. On display at CeBIT are the 2-bay AS-302T and 4-bay AS-304T. The two are positioned a notch below the 2 GHz Atom dual-core powered AS-602T and AS-604T. The two feature single gigabit Ethernet interfaces, a couple of USB 3.0 and USB 2.0/1.1 ports, and HDMI display outputs. The company's ADM 1.0 "Dolphin" interface is standard issue. The two are expected to launch some time in June.Source: Hardware.info

With consumers increasingly sharing and viewing content among different devices, Intel Corporation today introduced storage solutions based on the Intel Atom media processor CE5300 series. The new low power system-on-chip (SoC) enables high definition (HD) video to be simultaneously watched on smartphones, tablets and other smart devices, in real time, while also shared with consumer devices such as a Smart TV. "Streaming content across numerous mobile devices, not just from the cloud but locally, has become a common practice for today's consumers," said Bev Crair, general manager, of Intel's Storage Division. "New storage solutions based on the Intel Atom CE5300 series elevate this to a whole new level by making it simple to 'browse, click, and play'. The new SoC provides an excellent foundation for creating compelling entertainment experiences."

The powerful, dual-core Intel Atom CE5300 series delivers simple application and I/O support, making it ideal for synchronizing and streaming video content without compromising power for the performance necessary to allow seamless I/O and media transcoding. Storage solutions based on the Intel Atom CE5300 series allow consumers to easily set up all of their media in one place and avoid capacity limitations of mobile devices. They can use their storage system either as an iTunes server or DLNA (Digital Network Living Alliance) media server, and access that content from their mobile device of choice. Users can also simultaneously transcode 1080p video content to a smartphone, tablet, TV, Ultrabook or other smart device. The media processor system intelligently adapts to the screen resolution for each of these devices.

Thecus releases an all new 2-bay N2520 and 4-bay N4520 NAS server to lead the competition. The latest 2 and 4 bay NAS are designed to offer a revolutionary experience to the NAS industry. It utilizes the latest Intel Atom processor with 1GB RAM (N2520) and 2GB RAM (N4520). In addition, superspeed USB 3.0 fosters quick transfers, HDMI output is convenient for multimedia playback and McAfee Antivirus protection is to keep your NAS operating smoothly. The past proves merit; innovative technologies have been utilized to develop the new N2520/N4520 NAS to serve one single purpose: improve user experience and satisfaction.

"The integration of the new Intel Atom processor CE5315 and Thecus award-winning NAS is truly a revolution. We are proud to be the initial storage manufacture to embed Intel's first SoC storage dedicated chip, said Florence Shih, General Manager of Thecus. This pairing is phenomenal because it offers a new energy efficient, multimedia powerhouse and performance driven NAS solution to the storage industry."

Ahead of its unveiling last week, it was expected that Sony's PlayStation 4 console would be driven by little more than an AMD A-Series "Trinity" APU. It ended up being a lot more than that. The custom-design SoC that drives the next-generation console is a joint effort between AMD and Sony, which integrates an 8-core x86-64 CPU based on the company's new "Jaguar" micro-architecture; a GPU based on its Graphics CoreNext technology; a GDDR5 integrated memory controller, and certain enhancements by Sony. In an interview with The Inquirer, the company hinted that it's interested in porting the SoC over to the PC platform, minus Sony's share of the development.

GLOBALFOUNDRIES today announced additional enhancements to the foundry's 55-nanometer (nm) Low-Power Enhanced (LPe) process technology platform – 55nm LPe 1V – with qualified, next-generation memory and logic IP solutions from ARM. The 55nm LPe 1V is the industry's first and only enhanced process node to support ARM's 1.0/1.2V physical IP library, enabling chip designers to use a single process that supports two operating voltages in a single SoC.

"The key advantage of this 55nm LPe 1V offering is that the same design libraries can be used whether you are designing at 1.0 voltage or 1.2 voltage power option," said Bruce Kleinman, Vice President of Product Marketing at GLOBALFOUNDRIES. "What it means is that same set of design rules and models can be adopted, with no extra mask layer or special process required. This translates into cost saving and design flexibility without compromising on the power and optimization features."

AMD (NYSE: AMD) announced today that Bernd Lienhard, 48, has joined the company as corporate vice president and general manager of its Client Business Unit, reporting to Dr. Lisa Su, senior vice president and general manager, Global Business Units. In his role, Lienhard will apply his 22 years of experience in the semiconductor industry to lead AMD's client business as it expands its product lineup to include differentiated system-on-chip (SoC) solutions targeted at high-growth mobility and traditional client markets.

"A pivotal part of AMD's ability to win in high-growth markets is having the right leadership team in place with a diversity of semiconductor industry knowledge. Bernd's track record and experience translating business strategy into operational execution across large teams makes him the ideal leader for our client business," said Dr. Su. "Bernd's deep background of growth across a wide range of markets will accelerate our client business as we bring our strongest-ever line-up of APUs and first SoCs to market in 2013 and continue our expansion into ultraportable and ultra low-power form factors."

Intel Corporation today announced that its board of directors promoted five corporate officers and elected three new corporate vice presidents. William M. Holt, 60, was elevated from senior vice president to executive vice president. He is general manager of the Technology and Manufacturing Group and jointly oversees all technology development and manufacturing activities across the company. Holt joined Intel in 1974, was named a senior vice president in 2006, and is based in Hillsboro, Ore.

Thomas M. Kilroy, 55, was promoted from senior vice president to executive vice president. He is general manager of Intel's Sales and Marketing Group and is responsible for all of the company's sales and marketing efforts worldwide. Kilroy joined Intel in 1990, was named a senior vice president in 2010, and is based in Hillsboro, Ore.

AMD today announced that Charles Matar and Wayne Meretsky have joined the company to assume critical new engineering leadership roles driving hardware and software intellectual property (IP) development for AMD's system-on-chip (SoC) solutions. Matar will draw upon his expertise in SoC and processor design to lead AMD's SoC methodology and client SoC execution. Meretsky will lead the company's software development, ensuring tools will be in place that will enable developers to take advantage of the compute power in AMD's SoC designs.

"Charles and Wayne will serve as key members of our engineering brain trust, bringing with them years of expertise in SoC design and developing 64-bit software ecosystems, respectively," said Mark Papermaster, AMD Chief Technology Officer. "The fact that these computing experts have returned to the company underscores AMD's unique position and opportunity, based on differentiated IP, to take a leadership position in low-power clients and dense cloud servers."

Intel's known lineup of low-power Atom processors based on the "Silvermont" micro-architecture spans across the "ValleyView" line of chips for tablets, nettops, and embedded systems, "Avoton" line for micro-servers, and a third line that completes the triad, "Rangeley." Designed for the networking and communications market, such as high-density switches, internet- and telephone-exchanges, etc., these chips are the first Atom-branded products to pack up to eight x86 CPU cores.

The eight-core chips are built into a single-chip SoC design. The cores feature out-of-order execution, much like "Avoton," CPU clock speeds of up to 2.40 GHz, and an instruction-set that's carefully measured for Rengeley's target application, which includes SSE4.1/SSE4.2, AES acceleration, VT-x, and x86-64. Rangeley is also among the first Atom chips to feature a dual-channel DDR3 integrated memory controller, supporting DDR3-1600 MHz, blurring the lines between it and other Intel processors. Thanks to out-of-order execution, the chip gains a 35 percent performance increment over previous-generation "Saltwell" architecture. Since it's an SoC, its core-logic is completely integrated into the CPU package. Connectivity includes PCI-Express 2.0 (a total of 16 lanes spread across 4 ports), two SATA 6 Gb/s ports, gigabit Ethernet MAC, and legacy I/O.Source: CPU World

Intel Corporation announced a collaboration with Facebook to define the next generation of rack technologies used to power the world's largest data centers. As part of the collaboration, the companies also unveiled a mechanical prototype built by Quanta Computer* that includes Intel's new, innovative photonic rack architecture to show the total cost, design and reliability improvement potential of a disaggregated rack environment.

"Intel and Facebook are collaborating on a new disaggregated, rack-scale server architecture that enables independent upgrading of compute, network and storage subsystems that will define the future of mega-datacenter designs for the next decade," said Justin Rattner, Intel's chief technology officer during his keynote address at Open Computer Summit in Santa Clara, Calif. "The disaggregated rack architecture includes Intel's new photonic architecture, based on high-bandwidth, 100 Gbps Intel Silicon Photonics Technology, that enables fewer cables, increased bandwidth, farther reach and extreme power efficiency compared to today's copper based interconnects."

VIA Technologies, Inc, a leading innovator of power efficient computing platforms, today announced the VIA ARMOS-800, an ultra-compact, fanless system designed around the tiny VIA VAB-800 Pico-ITX board. The VIA ARMOS-800 provides embedded customers with a ruggedized system that delivers advanced multimedia features in an extremely power efficient design for a diversified range of embedded applications.

Featuring an 800MHz Freescale ARM Cortex-A8 SoC with two integrated GPUs for dual display support, the VIA ARMOS-800 is optimized for both performance and power to meet the high-end demands of advanced industrial and in-vehicle applications. Boasting a ruggedized, fanless system design with a wide operating temperature range from -40°C up to 80°C, the VIA ARMOS-800 delivers a typical power consumption of a mere 3.14W TDP.

Intel Corporation executives held a press conference today to outline a plan to accelerate new mobile device experiences across the company's growing portfolio of smartphone, tablet and Ultrabook offerings.

The announcements included a new smartphone platform for emerging markets, details on a forthcoming 22 nm quad-core SoC for tablets, and more personal and intuitive Ultrabook devices in innovative convertible designs were outlined by Mike Bell, vice president and general manager of the Mobile and Communications Group, and Kirk Skaugen, vice president and general manager of the PC Client Group at Intel.

It's no secret that nearly all Intel Core processors are carved out of essentially one or two physical dies, be it the "2M" die that physically features four cores and 8 MB of L3 cache, or the "1M" die, which physically features two cores and 4 MB of L3 cache. The two silicons are further graded for energy-efficiency and performance before being assigned a package most suited to them: desktop LGA, mobile PGA, mobile BGA, and with the introduction of the 4th generation Core "Haswell," SoC (system on chip, a package that's going to be a multi-chip module of the CPU and PCH dies). The SoC package will be designed to conserve PCB real-estate, and will be suited for extremely size-sensitive devices such as Ultrabooks.

The third kind of grading for the two silicons relates to its on-die graphics processor, which makes up over a third of the die area. Depending on the number of programmable shaders and ROPs unlocked, there are two grades: GT2, and GT3, with GT3 being the most powerful. On the desktop front (identified by silicon extension "-DT,") Intel very much will retain dual-core processors, which will make up its Core i3, Pentium, and Celeron processor lines. It will be lead by quad-core parts. All desktop processors feature the GT2 graphics core.

Samsung Electronics Co., Ltd., a global leader in advanced semiconductor solutions, today announced that it reached another milestone in the development of 14-nanometer (nm) FinFET process technology with the successful tape-out of multiple development vehicles in collaboration with its key design and IP partners. In addition, Samsung has signed an agreement with ARM for 14 nm physical IP and libraries. This agreement is the latest in a series from Samsung and ARM that has delivered production proven SoC enablement. Samsung, together with its ecosystem partners, is in a position to offer leading edge customers a robust design infrastructure to drive an ever expanding advanced mobile SoC market.

"As we move closer to true mobile computing, chip designers are eager to take advantage of the gains in performance and significantly lower power of 14 nm FinFET to deliver PC like user experience on a mobile device," said Dr. Kyu-Myung Choi, senior vice president of System LSI infrastructure design center, Device Solutions Division, Samsung Electronics. "The design complexities at 14 nm require complete harmony between the process technology, design methodology, tools and IPs. We are synchronizing all the key elements so our customers can deliver their newest chips to market quickly and efficiently."

Intel Corporation introduced the Intel Atom processor S1200 product family today, delivering the world's first low-power, 64-bit server-class system-on-chip (SoC) for high-density microservers, as well as a new class of energy-efficient storage and networking systems. The energy-sipping, industrial-strength microprocessor features essential capabilities to achieve server-class reliability, manageability and cost effectiveness.

"The data center continues to evolve into unique segments and Intel continues to be a leader in these transitions," said Diane Bryant, vice president and general manager of the Datacenter and Connected Systems Group at Intel. "We recognized several years ago the need for a new breed of high-density, energy-efficient servers and other datacenter equipment. Today, we are delivering the industry's only 6-watt SoC that has key datacenter features, continuing our commitment to help lead these segments."

Intel's 22 nanometer tri-gate technology, which goes into building today's 3rd Generation Core desktop and notebook processors, and soon the entry-level Pentium and Celeron ones, will make it to mobile SoCs (systems on chips), which will drive battery life-sensitive devices such as smartphones and tablets. Intel announced that development of such chips is in progress, speaking at the 2012 International Electron Devices Meeting. The new 22 nm SoCs could feature anywhere between 20 to 65 percent higher performance than today's 32 nm low-power chips. The new chips will allow Intel to take on mid- and high-grade ARM SoCs. Intel didn't go into the specifics.Source: C|Net

Intel will be capable making chips on the 14 nanometer silicon fabrication process, in 18-inch diameter wafers, "in two years," as development of the technology and machinery to make it happen is making good progress, according to company CTO Justin Rattner. He noted that Intel's aggressive tech advancement will keep Moore's Law relevant for at least the next 10 years. By the end of 2013, Intel's D1X Fab in Oregon, Fab 42 in Arizona, in the US, and Fab 24 in Ireland will begin producing batches of simple chips such as P1272 and P1273 series SoCs. After 14 nm, development for 10 nm, 7 nm, and 5 nm will follow, in order.

Source: DigiTimes