Introduction

In this article, which our team will regularly update, we will maintain a growing list of information pertaining to upcoming hardware releases based on leaks and official announcements as we spot them. There will obviously be a ton of rumors on unreleased hardware, and it is our goal to—based on our years of industry experience—exclude the crazy ones. In addition to these upcoming hardware release news, we will regularly adjust the structure of this article to better organize information. Each time an important change is made to this article, it will re-appear on our front page with a "new" banner, and the additions will be documented in the forum comments thread. This article will not leak information we signed an NDA for.

Feel free to share your opinions and tips in the forum comments thread and subscribe to the same thread for updates.

Last Update (November 4th):

• Updated AMD Zen 6
• Added AMD Ryzen Z3
• Updated AMD Ryzen 7 9700X3D
• Updated AMD Zen 2 / Zen+ Revival Processors
• Updated AMD Zen 7
• Updated Intel Diamond Rapids
• Added Intel Coral Rapids
• Updated Intel Nova Lake
• Updated Intel Razor Lake
• Updated Intel Raptor Lake Next
• Added Intel Moon Lake and Wildcat Lake Refresh
• Added NVIDIA GeForce RTX 5090 End of Life
• Updated NVIDIA GeForce RTX 5080 24 GB
• Updated NVIDIA GeForce RTX 5080 Super, 5070 Ti Super, 5070 Super
• Updated NVIDIA GeForce RTX 60-series (Rubin)
• Updated NVIDIA Vera Rubin
• Added Intel GPU D-Series "Crescent Island"
• Updated AMD RDNA 5
• Updated AMD UDNA
• Updated Intel Z990
• Updated Intel Z970
• Updated Intel B960
• Updated Intel Q970
• Updated LPDDR6 Memory
• Updated HBM4 Memory
• Updated HBM4E Memory
• Updated HBM5 Memory
• Added NVIDIA NVHBM Memory
• Added Samsung zHBM Memory
• Added Kepler Computing FeRAM Memory
• Added 3D DRAM
• Added YMTC LPDDR5X
• Updated Qualcomm HBC Memory
• Updated Sony PlayStation 6
• Updated Microsoft Xbox "Project Helix"
• Updated Valve Steam Deck 2
• Updated Nintendo Switch 2 Updates
• Updated TSMC 2 nanometer
• Updated TSMC 1.6 nanometer
• Updated TSMC 1.4 nanometer
• Updated Intel 18A-P
• Updated Intel 14A
• Updated Samsung 2 nanometer
• Updated Samsung 1 nanometer
• Updated Rapidus 2 nanometer
• Updated Elon Musk "Terafab"
• Added GlobalFoundries FDX Fusion
• Added Chinese Domestic Lithography
• Added Nanya Fab5A EUV DRAM
• Updated Hynix HBF High-Bandwidth Flash
• Updated Toshiba XL-Flash
• Updated Kioxia / Sandisk BiCS10 332-layer 3D NAND Flash
• Added Micron G11 400-layer 3D NAND Flash
• Added Seagate 50 TB HAMR Hard Drives
• Updated UFS 5.0
• Removed launched products: AMD Ryzen AI Max+ PRO "Gorgon Halo", AMD Ryzen 9 9955HX3D, AMD Radeon RX 9050, Intel Twin Lake, NVIDIA N1X, NVIDIA DLSS 4.5 Ray Reconstruction, NVIDIA DLSS 5, Next-Gen DirectX Ray Tracing, Valve Steam Frame; Removed canceled Intel High-End Battlemage / Arc B770

Processors

AMD Ryzen 9 Pro 9965X3D

• 16 cores #
• 170 W TDP #
• Officially announced as part of expanded Ryzen PRO 9000 lineup with 6 new SKUs #
• 32 threads, up to 5.5 GHz boost, 128 MB L3 cache (3D V-Cache) #
• Also includes Ryzen 7 PRO 9755X3D (8 cores, 96 MB L3, 120 W) #
• Launching H2 2026 #

AMD Ryzen 7 9750X / Ryzen 5 9650X

• Release Date: Unknown
• Ryzen 7 9750X: 8 cores / 16 threads, 4.20 / 5.60 GHz, 120 W TDP #
• Ryzen 5 9650X: 6 cores / 12 threads, 4.30 / 5.50 GHz, 120 W TDP #
• Zen 5, Socket AM5, 32 MB L3 cache #
• Higher clocks and TDP vs existing Ryzen 7 9700X / Ryzen 5 9600X #

AMD Ryzen Z3 [added]

• Release Date: Unknown #
• Handheld APU succeeding Ryzen Z2; both Z3 and Z3 Extreme use four "Zen 6" cores plus two "Zen 5" low-power cores for 6 cores / 12 threads #
• Up to 12 RDNA 4m CUs against the Z2 Extreme's 16 RDNA 3.5 CUs, but with RDNA 4-style matrix ALUs for FSR 4 #
• Z3 targets 15 W, Z3 Extreme 25 W #
• FF6 package, 25 x 25 mm - the same package tied to AMD's "Gainsborough", so attribution is unclear # #

AMD Zen 2 / Zen+ Revival Processors [updated]

• Release Date: possibly canceled. The Q2 2026 window passed with no launch and no further word on any of these SKUs #
• Ryzen 7 4700LE: Zen 2, 8 cores / 16 threads, 3.6 / 4.2 GHz, 65 W, Socket AM4, OEM-only #
• Ryzen 5 3501U: Zen+, 4 cores / 8 threads, 2.1 / 3.7 GHz, Radeon Vega 8 #
• Ryzen 3 3100U: Zen+, 2 cores / 2 threads, 1.9 / 3.2 GHz, Radeon Vega 8 #
• Mobile parts use a 15 W default TDP (12-35 W), DDR4-2400, FP5 package; aimed at low-cost notebooks and embedded #

AMD Zen 5c

• Release Date: Unknown
• 16 cores per CCD, in a single CCX that shares 32 MB L3 cache #
• Produced on a more advanced 3 nm node than Zen 5 #

AMD Zen 6 [updated]

• Release Date: launched July 23rd 2026 as 6th Gen EPYC "Venice" #
• Consumer Zen 6 (Ryzen "Medusa Point" mobile, "Olympic Ridge" desktop, Threadripper "Mustang Peak") not expected before CES 2027 #
• Codename: Morpheus #
• Codename: Sound Wave #
• Codename: Medusa Point (laptop) #
• Medusa Point uses soldered BGA, similar in size and Z-Height as Strix Point #
• Medusa Halo: 24 cores + 48 RDNA 5 CUs #
• Medusa Halo uses LPDDR6 memory #
• Another leak suggests bigger footprint BGA FP10 with 25 x 42.5 mm #
• Codename: Olympic Ridge (desktop) #
• Olympic Ridge supports Socket AM5 #
• October 2025 another confirmation that Zen 6 Olympic Ridge runs on AM5 #
• Gator Range for gaming laptops 55 W+ #
• Gator Range in 2027 #
• Bumblebee for value #
• 10% IPC increase over Zen 5 #
• Targets 1% lows and in-game stuttering through CPPC Performance Priority, HighestFreq and FloorPerf, steering power to the cores a game actually uses #
• Not sure if one CCX or two 16-core CCX's #
• Server codename: Venice #
• EPYC uses Socket SP7 #
• CCDs built using TSMC N2P process #
• Medusa point uses N2P compute tile + N3P I/O tile #
• 12 Zen 6 cores per CCD, in a single CCX, sharing an L3 cache of 48 MB #
• Another leak suggests 32-core CCD #
• Up to eight CCDs per EPYC CPU #
• 128 MB L3 per CCD #
• Medusa Point laptops will use RDNA 4 iGPU and an updated NPU in the IO die #
• Another leak suggests RDNA 3.5 iGPU GFX1153 for Medusa and RDNA 4 for Olympic #
• A newer leak suggests RDNA 4m iGPU GFX1170 #
• Could possibly introduce low power island CCX with Zen 6c #
• Zen 6c CCD will have 2 MB L3 cache #
• iGPU has 16 CUs #
• 3D V-Cache works the same as on Zen 5 #
• IO die is expected to be built using Samsung 4LPP # #
• Could also be built using TSMC N5 or N4P #
• Another leak suggests TSMC 2 nm for CCDs and 3 nm for IOD #
• Higher memory speeds supported at 1:1, over 10 GT/s with 1:2 # #
• 16- channel memory (SP7), 12-channel memory (SP8) #
• EPYC SP7: 600 W, SP8: 350-400 W #
• Will be supported on motherboards with 32 MB and 64 MB BIOS chips #
• CUDIMM support #
• New instructions: AVX512_BMM, AVX512_FP16, AVX_NE_CONVERT, AVX_IFMA, and AVX_VNNI_INT8 #
• OpenSIL support in 2026 #
• Medusa Point ES spotted on Geekbench: 10 cores, 32 MB L3 #
• Medusa Point ES matches Strix Point performance at half the clock speed #
• "Medusa Point" 10-core engineering sample reappears on Geekbench with improved performance, roughly 29% single-core and 22% multi-core over Strix Point #
• Additional RDNA 4m iGPU targets: GFX1171 and GFX1172 #
• HIPRT 3.2 names "Medusa" support for gfx1170, gfx1171 and gfx115E; the last is RDNA 3.5 family, so at least one Medusa part may keep RDNA 3.5 graphics #
• RDNA 4m is adapted RDNA 3.5 with INT8/FP8 for FSR 4 support #
• AMD plans to use RDNA 3.5 / RDNA 4m iGPU through 2029 #
• Zen 6 PQOS ISA extensions detailed: GLBE, GLSBE, PLZA #
• Second, lighter IBS Memory Profiler samples only data memory accesses, handing the kernel the physical address and whether the data came from DRAM or CXL, for tiered-memory page promotion #
• X970E chipset confirmed: reuses Promontory 21 silicon from ASMedia, new 4 nm client I/O die with native CUDIMM and CAMM support #
• EXPO 1.2 launched with CUDIMM profiles; full CUDIMM support requires Zen 6 #
• EPYC "Verano" confirmed as Zen 6, specialized for AI infrastructure. EPYC 9006 LP: 72 cores / 144 threads up to 5.00 GHz, 24-channel LPDDR5X via SOCAMM2, 112 Gbps-per-pin xGMI to Instinct MI455X, BGA rather than socketed, systems H2 2027 # #
• Verano reaches up to 192 cores: eight Zen 6 CCDs, two I/O dies, four LPDDR5X controllers, same TSMC N2 as Venice, paired with Instinct MI500, on SP8 rather than Venice's SP7 #
• A Dynatron cooler listing names "Socket SB1" for Verano, with the "B" possibly indicating a BGA package #
• EPYC "Venice" Zen 6c up to 256 cores / 512 threads; regular Zen 6 up to 96 cores / 192 threads #
• Meta confirmed as lead customer for Venice and Verano EPYC CPUs #
• EPYC "Venice" ramping high-volume production on TSMC N2, the first HPC product on the 2 nm node #
• EPYC "Venice" confirmed to launch July 22-23, 2026 at AMD's Advancing AI event; first HPC product on TSMC N2, up to 256 cores, Socket SP7, 16-channel memory, PCIe Gen 6 #
• Microsoft Azure to deploy EPYC "Venice" in new HDv2/HXv2 VMs; AMD "Helios" racks pairing Venice with Instinct MI455X ship in H2 2026 #
• Four EPYC 9006 lines: SP7 mainline, SP8 for performance per node, 9006X SP7 for HPC with larger caches, and 9006 LP "Verano" for AI host nodes on LPDDR #
• "Venice-X" HPC parts: up to 1,152 MB L3 per socket. SP7 gets 16-channel DDR5 with native DDR5-8000 RDIMM and MRDIMM to DDR5-12800; select SKUs add a 24-channel LPDDR5X interface with field-replaceable SOCAMM2 modules #
• 31 SKUs, from $700 for the 8-core EPYC 9016 to $14,904 for the 256-core EPYC 9996 (2.55 / 4.10 GHz, 1 GB L3, 600 W default, configurable 400-600 W) #
• Nine SP7 chips from the 64-core 9556 at $8,008; 22 SP8 chips up to the 128-core 9746 at $11,679. SP7 systems Q4 2026, SP8 H1 2027 #
• "TDP" retired in favour of "Default CPU Power" #
• A Geekbench 7 listing for the EPYC 9996 puts Zen 6c about 16.5% ahead of Zen 5 in single-core at a matched 4.1 GHz, winning all 15 subtests by 8.2% to 25.7%. The listing has since been pulled #
• AMD claims the 256-core EPYC 9996 is 2.24x an 88-core NVIDIA Vera platform in SPECrate 2026 Integer, and 2.4-3.7x a Xeon 6980P in server workloads #
• Socket AM5 platform support confirmed through 2029, implying at least one Zen 6 desktop generation on AM5 #
• Ryzen 10000 "Olympic Ridge" desktop may replace the iGPU with an NPU (Copilot+ if over 40 TOPS); new client I/O die adds native CUDIMM/CAMM and EXPO 1.2 #
• AMD documentation lists Ryzen 10000 "Olympic Ridge" as AM5-compatible, and also lists "Medusa1", hinting at socketed Medusa APUs after Olympic Ridge #
• Linux 7.3 adds HSMP protocol v7 for Zen 6 Family 1Ah Model 80H plus new PMF driver features; dual-CCD desktop SKUs expected at 12, 16, 20 and 24 cores #
• AMD confirms Zen 6 keeps one common CCD shared between client and server #
• Ryzen Threadripper "Mustang Peak" (TR6) confirmed as Zen 6 with PCIe 6.0 and DDR5 on a new socket, replacing the 4844-pin TR5 #

AMD Zen 7 [updated]

• Release Date: 2027 #
• "Verano" originally assumed to be Zen 7, but now confirmed as Zen 6 specialized for AI #
• Zen 7 server codename and details not yet known
• Retains Socket SP7 infrastructure compatibility #
• CCD IP codenamed "Grimlock", up to 16 cores per CCD #
• "Grimlock" APUs are expected to carry a new "RDNA 5+" iGPU in 2029 #
• The APU roadmap is reportedly split: parts that do not need strong integrated graphics stay on RDNA 3.5 until 2029, while premium parts such as Medusa Halo get RDNA 5 #
• Reportedly uses TSMC A14 (1.4 nm) node #
• New ISA: AVX10, ACE matrix extensions, FRED, and ChkTag memory tagging #
• Exploring Powertech FOPLP (fan-out panel-level) packaging and next-gen 3D V-Cache #

AMD Socket AM6

• Release Date: 2030 #
• Number of pins increased to 2100 #
• Increased power delivery capability, up to 200 W #
• PCIe 6.0 support #
• Possibly more PCIe lanes #
• Same physical size as AM5, coolers will be compatible #
• Expected to launch with Zen 7 #

AMD Ryzen 7 9700X3D [updated]

• This made rounds on Reddit in November 2025 #
• Turned out it's a spoofed result and no such SKU exists #
• AMD shipped the Zen 4 Ryzen 7 7700X3D in its place to use up "Raphael" stock; a 9700X3D would have eaten into the "Granite Ridge" dies reserved for the 9800X3D and 9850X3D #

Intel Diamond Rapids [updated]

• Release Date: 2026 #
• Branded as "Xeon 7" #
• Up to 256 P-Cores: 16 core chiplets of 16 "Panther Cove" cores each, four chiplets per compute base tile # #
• HOT CHIPS package breakdown: two Fabric Hub Tiles, four CPU core base tiles on Intel 3-T, 16 core chiplets on 18A-P, up to 1.28 GB last-level cache per socket, PCIe Gen 6 #
• No SMT, so 256 cores and 256 threads; multithreading does not return until "Coral Rapids" #
• Powers Oracle's planned OCI X14 cloud instances #
• Two SKU ranges: one uses 8-channel DDR5, the other 16-channel DDR5 #
• As of Nov 2025 the 8-channel SKUs have been canceled #
• MRDIMM Gen 2 support, 12,800 MT/s #
• Panther Cove cores #
• 500 W per socket #
• Platform: Oak Stream #
• 18A process #
• Built on Intel's enhanced 18A-P node, in risk production; debuts 2027 #
• Intel APX support #
• Native support for TF32 and FP8 #
• LGA 9324 #
• Custom Xeons for NVIDIA with NVLink integration, for use in NVIDIA SuperPODs #

Intel Coral Rapids [added]

• Release Date: 2028 #
• Branded "Xeon 8", successor to Xeon 7 "Diamond Rapids" #
• Reinstates SMT across the Xeon line, confirmed by CEO Lip-Bu Tan; Diamond Rapids and Clearwater Forest both ship without it #

Intel Jaguar Shores

• Release Date: Mid-2026 #
• AI accelerator #
• Successor to Falcon Shores #
• Uses HBM4 memory #

Intel Nova Lake [updated]

• Release Date: early 2027, full details at CES in January #
• "DS" dual-compute-die samples restricted to a small test group, rollout from December 2026 #
• Launch roadmap leak: 28-core "DS" first in Q1 2027, "K" SKUs in Q2 2027, flagship 52-core dual-compute-die SKU by mid-2027 #
• Engineering samples ready as of Feb 2025 #
• Successor to Arrow Lake
• Core Ultra 300 Series #
• New P-Core "Coyote Cove" #
• Other leak: 16 Coyote Cove P-Cores and 32 Arctic Wolf E-Cores and 4 LPE cores #
• Also considering 28-core (8P + 16E + 4LPE), and 16-core (4P + 8E + 4LPE) SKUs #
• Up to 52 cores # #
• ES: Running 52 cores at 4.8 GHz #
• Engineering samples tested with AVX-512 and APX enabled: a 24-core at 3.4 GHz and a 28-core at 3.2 GHz #
• PassMark leak: 28-core at about 61,509 multi-thread, roughly 85% of a Ryzen 9 9950X3D, and 5,210 single-thread, ahead of the 285K. Memory Mark lands at 2,523 against about 3,500 for the 285K #
• Claimed gains over comparable Arrow Lake parts: 8-17% in single-thread, 15% in general-purpose workloads and up to 20% in gaming. The 17% figure applies only to the bLLC SKUs #
• Part of the gain comes from memory: Nova Lake runs DDR5-8000 out of the box against Arrow Lake's DDR5-6400 #
• NVL-SK: 2x (8P+16E), NVL-HX: 1x (8P+16E), NVL-S/NVL-H: 4P+8E, NVL-U: 4P+OE #
• Nova Lake AX: 8P, 16E, 4LPE, bigger iGPU with 384 EUs, LPDDR5X #
• Nova Lake HX: BGA2540 #
• Core Ultra 9: 16P, 32E, 4LP, 144 MB L3, 150 W #
• A more recent leak suggests 175 W power limit for the top SKUs #
• Top 52-core overclocking SKU draws up to 474 W in PL2 mode #
• 28-core bLLC SKU draws up to 296 W at PL2, about 18% over the Core Ultra 9 285K's 250 W #
• Core Ultra 7: 14P, 24E, 4LP, 120 MB L3, 150 W #
• Core Ultra 5 K and KF: 8P, 16E, 4LP, 72 MB L3, 125 W #
• Core Ultra 5 non-K Med: 8P, 12E, 4LP, 33 MB L3, 125 W #
• Core Ultra 5 non-K Value: 6P, 8E, 4LP, 24 MB L3, 65 W #
• Core Ultra 3 Med: 4P, 8E, 4LP, 18 MB L3, 65 W #
• Core Ultra 3 Entry: 4P, 4E, 4LP, 12 MB L3, 65 W #
• Four-digit Core Ultra 4000 naming, led by a Core Ultra 9 4970K BFC (8P + 16E + 4LPE, bLLC, 125 W, 32 EU iGPU), with a 24-core 4950K, a 24-core 4870K BFC, a 20-core 4850K and a 65 W 22-core Core Ultra 9 4900 BFC # #
• "BFC" is Intel's retail brand extension for the bLLC parts, alongside "K" and "KF" for unlocked multipliers #
• Four-digit naming extends to "Nova Lake-HX"; H-series and suffix-less mobile parts stay on three digits #
• Possibly 4-core variant for low power laptops #
• Unlike Lunar Lake, no on-package memory #
• Uses TSMC 2 nanometer process for the CPU tile # #
• Intel's first 18A-P client product, "tracking ahead of schedule" per CEO Lip-Bu Tan, with design wins expected at twice Panther Lake's launch count # #
• Intel Foundry builds 80-90% of the compute tiles, TSMC dual-sources the rest # #
• Panther Lake's 18A compute die reached about 80% yield on a 114.3 mm2 tile. Intel expects to end 2026 at roughly 40,000 18A wafers per month, 60,000 by end of 2027 and 80,000 in 2028 #
• A teardown of shipping Panther Lake silicon measures 18A at roughly TSMC N3E logic density and about 18.6% denser than Intel 3, but behind TSMC N3P, TSMC N2 and Samsung SF2 on peak density #
• The same teardown counts four stacked ribbons per RibbonFET transistor against three sheets on Samsung SF2, and NPU 5 taking 36.9% less area than Lunar Lake's NPU 4 at the same INT8 MAC count #
• Intel is converting some 18A capacity at its Oregon sites to Intel 3 to feed Xeon demand, taking wafers that "are generally going to build Panther Lake products", with the added Intel 3 capacity in production in H2 2027. Nova Lake on 18A-P is unaffected and still ahead of schedule #
• Substrates are a second constraint: much of Intel's planned 40% substrate capacity increase does not arrive until H2 2027 #
• Should be "quite a jump from Arrow Lake (ARL) in terms of MT performance" #
• Intel bLLC could be their X3D equivalent, offering bigger L3 cache for gaming performance #
• bLLC CPU has up to 14 P-Cores #
• Socket LGA1954 #
• Older coolers are compatible # #
• Also using Intel 14 A #
• DDR5 memory #
• Default DDR5 speed is 8000 MT/s #
• Chipsets: B960 #
• PCI Express 6.0 #
• New Gen 6 NPU, newer than Panther Lake #
• 74 TOPS NPU #
• AVX 10.2 and APX officially confirmed #
• AVX-512 returns to Intel client, supported on both Coyote Cove P-cores and Arctic Wolf E-cores #
• Windows 11 build 29695 adds an APX toggle. APX doubles general-purpose registers from 16 to 32 and cuts compiled instruction counts by around 10% #
• AVX10.2 is the vector target, which needs AVX-512 on both core types, so "Coyote Cove" P-cores and "Arctic Wolf" E-cores both get it #
• Xe3P iGPU # #
• RT support not available on all iGPU models #
• New NPU with over 100 TOPS IN8 #
• Compute tile: 110 mm² #
• bLLC tile: 150 mm² #
• Up to 700 W power with power limits disabled #
• Nova Lake-HX mobile: top config 8P+16E+4LPE, perf segment 6P+8E+4LPE #
• Top mobile part is the Core Ultra 9 4995HX: 8P + 16E + 4LPE with only 2 Xe3 GPU cores. The Core Ultra 9 4970H runs 4P + 8E + 4LPE with the 12-core Xe3P iGPU #
• First Nova Lake-H and HX laptops expected around CES 2027 #
• "Nova Lake-HX" die shot: 12 x 30 mm, 360 mm2 across six dies - a 104 mm2 TSMC N2P compute tile (8P + 16E, 14.8 x 6.6 mm), a 72 mm2 18A-P hub carrying the 4 LPE cores, a 58 mm2 18A-P peripheral tile, a 26 mm2 Intel 3-E graphics tile with 4 Xe cores, and two structural dies # #
• P-cores: Coyote Cove; E-cores: Arctic Wolf #
• Nova Lake-HX iGPU: Xe4 "Druid" with 2 Xe cores (minimal, designed for dGPU pairing) #
• Desktop iGPU confirmed as Xe3, display/media engine from Xe3P "Crescent Island" #
• Nova Lake-S desktop uses 2L-ILM socket mechanism for improved cooler contact #
• Linux 7.3 patches bring the number of supported Nova Lake-S GPUs to seven # #
• The 12 Xe3P desktop APU SKU (4P + 8E + 4LPE) is postponed to "Razor Lake". It was pinned at 40 W PL2 with 65 W reserved for PL3/PL4, two VCCGT phases, 20 MB GPU L2, and possible DDR5-8000 through CSODIMM # # # #
• Nova Lake-AX (48 Xe3 cores) variant appears on hold #
• Desktop core configs leaked: from 4P+0E+4LPE up to dual-die 16P+32E+4LPE #
• bLLC (big last-level cache): Intel's answer to AMD 3D V-Cache #
• Two mid-range 22-core SKUs (6P + 12E + 4LPE) carry 108 MB of bLLC gaming cache; one unlocked 125 W "K", one 65 W #
• NPU6 in all SKUs; Thunderbolt 5 / USB4 V2 support #
• LGA1954 intended to last through end of decade #
• Z970 chipset will absorb much of the current B860 segment, becoming the primary mainstream chipset #
• Intel plans to expand overclocking support to budget CPU SKUs, possibly starting with Nova Lake #
• Socket LGA1954 pictured in the flesh, confirms squarish 2L-ILM design; retains LGA1851 / LGA1700 cooler compatibility (min 35 lbs load) #
• Intel's published validation tool listing ties LGA1954 to Nova Lake-S; a leaked partner slide states the socket is kept for multiple generations # #
• Cleared USB-IF compliance (USB4 on two Nova Lake-H IDs, USB 3.2 Gen 2 on the PCH-S) and PCI-SIG PCIe 5.0 x16 certification #
• HWiNFO 8.53 beta adds qualification-sample support; Thermal Grizzly already sells LGA1954 water blocks # #
• "Nova Lake" Xeon E splits into P-core-only (4, 6, 8, 12, 16) and E-core-only (4, 8, 16, 32) SKUs with no hybrid configurations, on the W980 chipset #
• Intel's Robert Hallock confirms the new cores reach desktop before Xeon, the reverse of AMD's order #

Intel Bartlett Lake for Gaming

• Release Date: Unknown #
• CPU with 12 P-Cores #
• Bartlett Lake is already out for edge and networking applications, could come to gaming segment #
• Uses Socket LGA1700 #
• No E-Cores #
• Might be focused on OEM and embedded markets, not DIY retail #
• Top Bartlett Lake CPU available for sales as of March 2026 #
• Won't run on consumer motherboards #
• Modder got Bartlett Lake to run on consumer Z790 motherboard via BIOS mod #
• Core 9 273PQE booted Windows 11 on Z790 #
• Now also offered as a Xeon 6300 entry-level server CPU: up to 12 "Raptor Cove" P-cores, 36 MB cache, ECC support, drop-in on LGA1700 Xeon 6300 platforms #

Intel Raptor Lake Next [updated]

• Release Date: 2027 #
• New Socket LGA1700 desktop processors aimed at DDR4 users amid the DDR5 pricing crisis (Arrow Lake lacks DDR4 support) #
• Also expanding to gaming notebooks — an HX-segment part (8P + 16E, 32 threads, Intel 7, 55 W base) to soak up DDR4 SODIMM inventory #
• Likely branded under the Core Series 3 scheme without "Ultra" (no integrated NPU) #
• Top SKU expected at 8P+8E (not the 8P+16E that Raptor Lake-S silicon physically has), spanning entry-thru-performance segments #
• Four SKUs in shipping manifests, two identified: 99DLMV at 16 cores (8P + 8E), 3.5 GHz, 30 MB cache, up to 125 W; 99DLMT at 20 cores (8P + 12E), 2.1 GHz, 33 MB cache, 65 W. 99DLMW and 99DLMX unidentified #
• The 8P + 8E part replaces the Core i5-14600K, with more 125 W and 65 W desktop SKUs planned #
• Mobile branding is Core 2000HX without "Ultra", up to 8P + 16E, separating the Intel 7 dies from Nova Lake-HX's Core Ultra 4000HX naming #
• GIGABYTE has pushed BIOS updates across its entire B760 and H610 lineup for LGA1700 processors it says are "expected to launch in early 2027", covering DDR4 and DDR5 boards #
• Positioned below the next-gen Core Ultra "Nova Lake-S" #

Intel Beast Lake

• Release Date: 2026 or 2027 #
• Successor to Arrow Lake #
• Uses Royal Core 1.1 P-Core architecture #

Intel Razor Lake [updated]

• Release Date: Unknown #
• Intel Core Ultra 400 Series #
• "Razor Lake-AX" rated at 700 TOPS of on-die AI compute, 3.88x Panther Lake's 180 TOPS, per Intel SVP Cho Min-sung #
• Two iGPU tiers: a 16-core and a flagship 32-core Xe3 configuration #
• "Razor Lake-AX" uses a BGA-4326 package with EMIB and Foveros 3D, for 2028. "Nova Lake-AX" is on hold #
• Preliminary support landed in HWiNFO, full support in v8.51 #
• At least part of production moves to TSMC N2X, the high-frequency variant of N2; bLLC comes to laptop SKUs #
• Inherits the shelved Nova Lake-S desktop APU SKU with 12 Xe3P cores #
• "Razor Lake-AX" variant to feature up to 32 Xe3 iGPU cores (~162 mm² GPU die), BGA-4326 package #
• On-package LPDDR5X/LPDDR6 memory returning with Razor Lake-AX #
• Original "Nova Lake-AX" plan with 48 Xe3 cores shelved; "AX" suffix moves to Razor Lake instead #
• Expected a year after Nova Lake, so late 2027 into 2028 #

Intel Serpent Lake

• Release Date: Unknown
• First Intel x86 SoC with integrated NVIDIA GeForce RTX GPU #
• Joint Intel-NVIDIA collaboration chip, similar concept to "Kaby Lake G" with AMD #
• Intel CEO Lip-Bu Tan confirmed ongoing product development #
• Report: Intel to introduce processors with NVIDIA integrated GPUs by CES 2028, possibly a Panther Lake or Nova Lake derivative with an NVIDIA GPU tile #

Intel Arrow Lake "KS"

• Release Date: 2025 at least #
• Haven't heard from that for a long time, so might be canceled
• Could be called Core Ultra 9 295K #

Intel Grand Ridge

• Release Date: Unknown, could be canceled
• Produced on 7 nm HLL+ process
• Successor to Atom "Snow Ridge"
• 24 cores across 6 clusters with 4 cores each
• 4 MB L2 per cluster, plus L3 cache
• Uses Gracemont CPU core
• Dual-channel DDR5
• PCI Express Gen 4 with 16 lanes
• Sources

  
  www.techpowerup.com/270718/intel-readies-atom-grand-ridge-24-core-processor-features-pcie-4-0-and-ddr5
  

Intel Moon Lake and Wildcat Lake Refresh [added]

• Release Date: Unknown #
• "Moon Lake" (MNL) is a pure low-power SoC: no P-cores, up to four "Darkmont" LPE-cores on Intel 18A, about 6 W base power, BGA1516 package #
• Aimed at embedded devices such as NAS boxes; reads as the successor to the "Alder Lake-N" N-series #
• "Wildcat Lake Refresh" raises the Core 300 series to 4 "Cougar Cove" P-cores, keeps 4 Darkmont LPE-cores and up to 2 Xe3 GPU cores, and adds vPro #
• Both share Wildcat Lake's BGA1516 package and Intel 18A node #
• Wildcat Lake itself is shipping and Intel says it is sold out, appearing in the Dell 14S, the Xiaomi Redmi Book 14 / 16 2027, Biostar's EdgeComp MS-U320 and Zotac's fanless ZBOX CI431 / CI451 / CI471 nano # # # # #
• Retail Wildcat Lake SKUs: Core 3 304 at 1P + 4LPE and one Xe core, Core 5 320 and Core 7 350 at 2P + 4LPE and two Xe cores, all 18A, 6 MB cache, 15 W base and 35 W turbo, 15 to 17 TOPS #

Intel Griffin Cove

• Codename for new P-Core #
• Great-grandchild of Lion Cove #

Zhaoxin CPUs

• Release Date: Unknown #
• KH-50000: 96 cores, 2.2 to 3.0 GHz, SMT support unknown. 384 MB L3, 12-channel DDR5 memory, 128 lanes PCIe 5.0, up to 4 sockets #
• KX7000N: adds NPU, core count higher than eight, PCIe 5.0 #
• 12 Compute dies with a large central IO die #
• 12-channel DDR5 support #
• 128 lanes of PCIe 5 + 16 lanes Gen 4 #

Graphics / GPUs

NVIDIA GeForce RTX 5090 SE

• Release Date: Unknown #
• New SKU positioned between the RTX 5080 and RTX 5090, based on a cut-down GB202 #
• 110 of 192 SMs enabled: 14,080 CUDA cores, 110 RT cores, 440 Tensor cores #
• 384-bit GDDR7, 32 GB using mixed 24 Gb and 16 Gb chips, ~500 W TGP #
• Target price around $1,500 #

NVIDIA GeForce RTX 5090 End of Life [added]

• Status: unconfirmed and still moving. NVIDIA denies it, the supply chain says otherwise # #
• GB202 is being redirected to the far pricier RTX PRO cards; a factory notice reportedly reads "5090 EOL, 5080 24GB ready" #
• Discontinuation dates are claimed for the first half of January 2027, covering both the RTX 5090 and the RTX 5080 16 GB #
• NVIDIA SVP Jeff Fisher denied on October 17 that the card is discontinued, saying supply is simply tight #
• Board partners cannot buy GB202 bundled with 32 GB of GDDR7 any more, and unlike previous shortages, backorders are blocked #
• One cooler OEM has taken no RTX 5090 heatsink orders at all for Q2 2027, and two partners cut their Q1 2027 forecasts sharply #
• Against that, Zotac restocked the RTX 5090 Solid OC in Japan after the reports, at 1,190,000 JPY, so allocation may simply be regional #
• The RTX 5080 has now vanished from NVIDIA's US Marketplace too, about two weeks after the RTX 5090, leaving the RTX 5070 Ti as the fastest card on the store. The UK Marketplace still lists both, and NVIDIA's own RTX 5080 page still reads "Starting at $999" #
• NVIDIA is reportedly cutting off RTX 5080 16 GB and RTX 5090 D V2 supply to China, leaving the 24 GB RTX 5080 as the only flagship there. Remaining 16 GB inventory is put at about two months #
• Pricing has gone with it: the RTX 5090 now sells for about 262% over its $1,999 MSRP worldwide, with the cheapest in-stock US card at $9,400, and another round of hikes up to $500 per card was scheduled for early November # #
• Board partners in China are redirecting buyers to the revived RTX 3060 12 GB and RTX 3050 as RTX 50-series inventory runs out #

NVIDIA GeForce RTX 5060 / 5060 Ti 9 GB

• Release Date: May-June 2026, possibly Computex #
• 9 GB GDDR7 using three 3 GB memory chips #
• 96-bit bus (down from 128-bit), reduced bandwidth #
• RTX 5060 Ti 8 GB supply paused in late April for transition #

NVIDIA GeForce RTX 60-series (Rubin) [updated]

• Release Date: 2028 #
• GR20x is placed in 2028, with only select RDNA 5 parts arriving in 2027 # #
• The RTX 6060 is expected much later still, and may not match the PlayStation 6 #
• Memory vendors are reportedly planning 4 GB and 6 GB GDDR7 chips for 2027-28, while Micron's 2 GB GDDR7 parts reach end of life # #
• Based on "Rubin" graphics architecture #
• TSMC 3 nm FinFET variant #
• Chip naming: GR202 (flagship), GR203, GR205 #
• 6th Gen Tensor cores, 5th Gen RT cores #
• 100% RT / path tracing performance increase over RTX 50-series #
• 30-35% raster performance gains SKU-to-SKU #
• Clock speeds: high 2 GHz to low 3 GHz #
• RTX 6090: GR202, 192 SM, 512-bit GDDR7, 32 GB #
• RTX 6080: GR203, 320-bit GDDR7, 20 GB, 25%+ bandwidth increase over RTX 5080 #
• RTX 6070: GR205, 256-bit GDDR7, 16 GB, 33%+ bandwidth increase over RTX 5070 #
• AIC partner Palit confirms next-gen GALAX HOF and KFA2 variants already in development # #

NVIDIA GeForce RTX 5080 24 GB [updated]

• Release Date: Q1 2027, possibly announced at CES #
• 24 GB VRAM instead of 16 GB #
• 24 GB on the same 256-bit bus points to 3 GB GDDR7 modules in place of 2 GB ones #
• The launch was moved up to December 2026 or January 2027, with the RTX 5080 16 GB phased out in China #
• That window looks unreachable: board partners still have no GPU kits, and two months are now needed from receiving design information to launching a card. CES 2027 is the likely reveal, with availability a few weeks later #
• Positioned as the replacement for the RTX 5080 16 GB, and tied to the RTX 5090's end-of-life situation # #
• Expected to be expensive: China pricing is guessed at around 19,999 yuan #

NVIDIA GeForce RTX 5080 Super, 5070 Ti Super, 5070 Super [updated]

• Release Date: Not before 2027 #
• Could be canceled due to GDDR7 shortage #
• Board partners have received RTX 50 Super silicon, but the launch is held back by a 3 GB GDDR7 shortage as NVIDIA prioritizes AI GPUs #
• Not canceled, but Q3 2026 #
• Newer leak: 2027 at best #
• Older leak: Christmas 2025 #
• Using 24 Gbit (3 GB) GDDR7 memory chips #
• RTX 5080 Super: 24 GB GDDR7, 32 Gbps, 256-bit, 84 SMs, 10,752 cores, 415 W #
• RTX 5070 Ti Super: 24 GB GDDR7, 28 Gbps, 256-bit, 70 SMs, 8,960 cores, 350 W # #
• RTX 5070 Super: 18 GB GDDR7, 28 Gbps, 192-bit, 50 SMs, 6,400 cores, 275 W # #
• Seasonic's PSU calculator lists the RTX 5080 Super (415 W), 5070 Ti Super (350 W), and 5070 Super (275 W) #
• Discontinuation dates claimed for the first half of January 2027 for both the RTX 5090 and the RTX 5080 16 GB, which would clear shelf space for a refresh #

NVIDIA GeForce RTX TITAN Blackwell

• Release Date: Unknown #
• Another leak suggests late 2026 #
• GB202-200-A1 GPU #
• Could use the full GB202 GPU #
• 24,576 CUDA cores, 768 Tensor cores, 192 RT cores, 768 TMUs, and 192 ROPs, besides 88 MB of L2 cache #
• 512-bit GDDR7 memory interface #
• 32 Gbps memory speeds #
• Two 12V-2x6 power connectors #

AMD Radeon RX 9040

• Release Date: Unknown #

Intel GPU D-Series "Crescent Island" [added]

• Release Date: announced October 2026, sampling now #
• Inference accelerator on Xe3P, not a gaming card: 32 Xe3P cores, 256 Vector engines, 256 XMX engines, 32 MB unified L2 # #
• XMX engines redesigned from Xe3's four-deep systolic array to 16-deep; FP4 alongside FP8, 1 MB register file and 512 KB L1 per core # #
• Up to 1.3 PetaFLOPS FP8, formats from FP4 to FP64, up to 1.5 TB/s memory bandwidth #
• 160 GB LPDDR5X on Intel-branded cards; ODMs may fit up to 480 GB. Some partner boards are claimed at 512 GB, which does not divide evenly across the 20 LPDDR5X sites on the leaked PCB # #
• 350 W, air-cooled, PCIe 5.0 x16, single 16-pin connector, so it drops into conventional servers without liquid cooling # #
• Media engine with four encoders and four decoders, but no display output - the silicon carries no graphics output elements at all #
• Top SKU is the D270; support has landed in the Intel media driver # #
• Leaked PCB shows the Xe3P die is larger than BMG-G31, with 20 LPDDR5X sites and a single 16-pin power connector #
• Xe3P skips Arc gaming GPUs entirely; no consumer discrete gaming card planned for this generation # #

NVIDIA Vera Rubin [updated]

• Release Date: 2026 #
• Six months ahead of schedule as of June 2025 #
• Successor to "Blackwell" #
• "Blackwell-Next" GPU appears in Linux kernel CXL patches #
• Named after the scientist Vera Rubin #
• Flagship GPU: R100, built on TSMC 3 nm EUV, chiplet design, CoWoS-L with HBM4 #
• Grace Rubin GR200 could be 3 nm #
• 8 stacks of HBM4 #
• NVIDIA detailed the "Rubin" GPU: two reticle-limited dies on an NV-HBI link, 336 billion transistors, up to 224 SMs, 288 GB HBM4 (12-Hi, 22 TB/s), up to 50 PFLOPS NVFP4, NVLink 6, and PCIe Gen 6 #
• NVLink 6 switches with 3600 GB/s #
• TSMC 3 nanometer N3P node #
• CoWoS-L packaging #
• Looks like Vera Rubin is actually a combination of CPU "Vera" and GPU "Rubin", for enterprise compute, not for consumers #
• VR200 samples shipped as of Feb 2026 #
• "Rubin Ultra" reportedly faces issues with CoWoS-L packaging (warping with 4 dies + 16 HBM4E) #
• TSMC exploring CoPoS alternative, pilot lines 2026, mass production late 2028-H1 2029 #
• Standard Rubin mass shipments set for summer 2026 #
• Dell PowerEdge XE8812 with Vera Rubin NVL4 (176 cores) available early 2027; powers the DOE "Doudna" supercomputer #
• Wistron's Fort Worth, Texas facility will mass-produce the Vera Rubin Superchip #
• Samsung HBM4 mass-production sales for Vera Rubin started February 2026 #
• SK hynix 192 GB SOCAMM2 now in mass production for Vera Rubin #
• SK hynix exploring Intel EMIB 2.5D packaging as alternative to TSMC CoWoS for HBM #
• Targets formally cut: HBM4 to 9.6 Gbps per pin, NVL72 memory bandwidth to 1,400 TB/s, NVLink per-GPU bandwidth to 1.5 TB/s (3 TB/s bidirectional), and the NVLink Nyquist target to 47 GHz, all for signal integrity #
• Leaves AMD's Helios rack ahead on paper: MI455X carries 432 GB HBM4 at 23.3 TB/s per GPU against Rubin's 288 GB at 19.2 TB/s, and 3.6 TB/s bidirectional UALoE per GPU against Rubin's 3 TB/s #
• "Rubin CPX" revived with 168 GB of HBM4 instead of 128 GB of GDDR7; racks hold 64 to 256 CPX GPUs, handling prefill and KV cache while regular Rubin handles decode. Eight CPX GPUs per tray cover 1.34 TB of long-context prefill #
• Samsung HBM4E has passed qualification testing for "Rubin Ultra" #
• Supermicro is shipping Vera Rubin NVL72 racks #
• NVIDIA is growing substrate capacity 2.5x in three years: IBIDEN's Ono plant tripling from Q1 2028, Samsung Electro-Mechanics joining, Unimicron adding from Q2 2027 #
• Amkor is to raise interposer wafer capacity more than 300% by end of 2028; test capacity doubles from 2026 to 2027; SPIL expands co-packaged optical engine output 15x by mid-2027 #
• Final test is a bottleneck of its own: Blackwell takes about four times Hopper's test time, and Rubin could need seven times #
• Successor "Feynman" moves to TSMC A16 with backside power delivery, SoIC 3D stacking and CoWoS-L or panel-level packaging; mass production H2 2028 #
• HBM4E initial samples going out to customers in Q2 2026 #
• "Vera" CPU benchmarked: 88 custom Armv9.2 "Olympus" cores / 176 threads, FP8, 1.2 TB/s bandwidth, up to 1.5 TB LPDDR5X (SOCAMM2), 450 W; about 11% ahead of the top EPYC and about 55% over the best single-socket Xeon #
• NVIDIA officially detailed the "Vera" CPU: 88 "Olympus" Armv9.2 cores with a neural branch predictor, 164 MB L3, a 3.4 TB/s coherency fabric, and up to 1.8x per-core performance over EPYC "Turin" #

AMD Navi 4c

• Release Date: Possibly canceled #
• Embraces chiplet design even more #
• Separate dies for Shader Engines (SED) and Multimedia & IO (MID) #
• Shader Engine Dies could be built on 3 nanometer TSMC #
• Uses an active interposer (AID) #

AMD RDNA 5 [updated]

• Release Date: H2 2027 at the earliest #
• Not before Computex 2027. "AT2" leads the stack, with "AT0", "AT3" and "AT4" a few quarters later in 2028. AT2 is likely a mid-range part, so the flagship may come second #
• A separate rumor puts full RDNA 5 and NVIDIA Rubin gaming cards in 2028, with only select RDNA 5 silicon in 2027 #
• Target clocks of 3.1 to 3.5 GHz, 4-14% over the RX 9070 XT's 2.97 GHz boost #
• GDDR7 now listed among supported VRAM types in the AMDGPU driver #
• First shipping silicon with RDNA 5 IP is not a Radeon: Samsung's Exynos 2700 on SF2 carries the Xclipse 970 with 8 WGPs, so 16 CUs #
• DCN6 display engine patches landed in the Linux kernel #
• Clean sheet design #
• Might not even have "RDNA" branding #
• Possible return to high-end: could feature 96 CUs and 384-bit memory #
• Codenames: Alpha Trion, Ultra Magnus, Orion Pax #
• Spotted in code update for LLVM gfx1310 target #
• GFX1310 codename confirmed #
• Full Dual-Issue VALU pipeline for Wave32, simultaneous X and Y ALU lane issue #
• FP32 compute utilization significantly improved over RDNA 3/4 #
• FSR Diamond announced for Xbox Project Helix, likely RDNA 5 / UDNA exclusive #
• AMD developing FSR Multi-Frame Generation (up to 8x); current RX 9000 cards may lack the required hardware flip metering, possibly needing RDNA 5 #
• Rumored to bring AMD's answer to DLSS 5, described as "Neural Lighting" and probably RDNA 5-only because the workload is heavy #
• AMD's tetrahedral cages technique cuts BVH memory about 47x and BVH update time about 90x on dense animated geometry: a 25,000-plant scene drops from 80 GB and over 300 ms per frame to 1.7 GB and 3.3 ms #

AMD UDNA [updated]

• Release Date: Unknown #
• AMD is expected to unify their RDNA and CDNA architectures into a single architecture #
• Improvements to RT performance #
• Will be used in next-gen Xbox and PlayStation 6 #
• Possible return to high-end: could feature 96 CUs and 384-bit memory #
• Support for 80 Gbit/s HDMI 2.2 #
• Four die sizes #
• Biggest core will have 96 CU #
• FSR Diamond announced for Xbox Project Helix #
• FSR Diamond expected to include multi-frame generation and neural rendering #
• FSR 4.1 has shipped to Radeon RX 6000 cards, all Strix and Gorgon APUs, the Ryzen Z2 handheld chips and Vulkan, across the 400-plus games that support FSR 3.1 or newer. Xbox Series X|S follows in the coming weeks # # #
• "FSR Diamond" teased as the next step, with machine-learning upscaling and multi-frame generation, tied to the Xbox "Project Helix" generation #

Chinese Lisuan LX 7G106 GPU

• Release Date: June 18, 2026 #
• Chinese-made discrete GPU, TSMC 6 nm #
• 24 TFLOPS FP32, 192 TMUs, 96 ROPs #
• 12 GB GDDR6, 192-bit bus #
• DirectX 12 (no ray tracing), Vulkan 1.3, AV1 decode up to 8K #

Imagination PowerVR on Windows

• Release Date: Unknown
• Imagination D-Series PowerVR GPU running on Windows with DX11, DX12, Vulkan 1.4, OpenGL 4.6 #
• Chinese manufacturer Xiang Dixian has shipped Fuxi A0 card based on this architecture #

Intel Celestial Architecture

• Release Date: Late 2025 or early 2026 #
• Could also be released in 2025 #
• Confirmed "in development" as of Jan 2024 #
• IP design is baked #
• Discrete GPU architecture
• Successor to "Battlemage" architecture
• Also called "Xe3 HPG"
• dGPU might be based on Xe3P instead of Xe3 #
• Fabricated on TSMC N3X (3 nm) # #
• Could also be fabricated using Intel in-house process #
• Targets "Ultra Enthusiast" segment
• 8192 shaders, 2x that of A770 #
• Sources

  
  www.techpowerup.com/292208/intel-targeting-2024-for-ultra-enthusiast-arc-celestial-gpus
  www.techpowerup.com/285760/intel-xe-hpg-graphics-architecture-and-arc-alchemist-gpu-detailed
  
• "Crescent Island" Xe3P skips Arc gaming GPUs and became the Intel GPU D-Series; see that section #

Intel Xe Next

• Release Date: 2026 or 2027 #
• Successor to Xe3P #
• Dedicated GPU #
• Likely manufacturing mix: Intel fabs + TSMC #
• HBM4 memory (Hynix) #
• Rack-scale accelerator designs targeting NVIDIA and AMD in data center market #
• Higher compute density, wider vector/matrix units, larger cache #

Intel Druid Architecture

• Release Date: Not before 2027
• Discrete GPU architecture
• Successor to "Celestial" architecture
• Also called "Xe Next HPG"
• Sources

  
  www.techpowerup.com/285760/intel-xe-hpg-graphics-architecture-and-arc-alchemist-gpu-detailed
  

Chipsets

Intel Z990 [updated]

• Release Date: Late 2026 (Nova Lake-S platform) #
• Flagship enthusiast chipset #
• DMI: Gen 5 x4 (128 Gbps per direction) #
• PCIe (chipset): 12x Gen 5 + 12x Gen 4 #
• CPU PEG: PCIe 5.0 x16 (x16 or x8/x8) #
• CPU NVMe: 2x M.2 Gen 5 supported #
• USB4 / TB4: 2x 40 Gbps from CPU #
• CPU OC: Multiplier + BCLK supported #
• Nova Lake-S reference Z990 board allows up to three 8-pin EPS connectors to feed the 474 W top SKU #
• At least five Z990 boards appeared in Taiwan and Vietnam customs records dated July 2026 #

Intel Z970 [updated]

• Release Date: Late 2026 (Nova Lake-S platform) #
• Enthusiast chipset below Z990 #
• Shares smaller PCH with B960 #
• DMI: Gen 5 x2 (64 Gbps per direction) #
• PCIe (chipset): 14x Gen 4 #
• CPU PEG: 1x PCIe 5.0 x16 #
• CPU NVMe: 1x M.2 Gen 5 x4 #
• USB4 / TB4: 1x 40 Gbps from CPU #
• CPU OC: Multiplier supported #
• Two ASRock boards, the Z970 LiveMixer WiFi and Z970 Pro-A WiFi, appear in Vietnamese customs records as PCBs shipped at the end of September 2026 #
• Expected to replace most of the market B860 covers today, which would put CPU multiplier overclocking on a mid-range chipset for the first time in years #
• Decenta's M26-NVLS-ATX09 LGA1954 board is offered with either Q970 or B960: 44 total lanes for Q970 (8 chipset PCIe 5.0 plus 12 PCIe 4.0) against 34 for B960 (no chipset PCIe 5.0, 14 PCIe 4.0). Four DDR5-6400 slots, 256 GB maximum #

Intel B960 [updated]

• Release Date: Late 2026 (Nova Lake-S platform) #
• Mainstream chipset #
• Shares smaller PCH with Z970 #
• DMI: Gen 5 x2 (64 Gbps per direction) #
• PCIe (chipset): 14x Gen 4 #
• PCIe 5.0 (chipset): None #
• CPU PEG: 1x PCIe 5.0 x16 #
• CPU NVMe: 1x M.2 Gen 5 x4 #
• USB4 / TB4: 1x 40 Gbps from CPU #
• CPU OC: Not supported #
• Decenta's M26-NVLS-ATX09 LGA1954 board is offered with either Q970 or B960: 44 total lanes for Q970 (8 chipset PCIe 5.0 plus 12 PCIe 4.0) against 34 for B960 (no chipset PCIe 5.0, 14 PCIe 4.0). Four DDR5-6400 slots, 256 GB maximum #

Intel Q970 [updated]

• Release Date: Late 2026 (Nova Lake-S platform) #
• Commercial desktop chipset #
• DMI: Gen 5 x4 (128 Gbps per direction) #
• PCIe (chipset): 8x Gen 5 + 12x Gen 4 #
• USB4 / TB4: 2x 40 Gbps from CPU #
• CPU OC: Not supported #
• Features: Intel vPro support #

Intel W980

• Release Date: Late 2026 (Nova Lake-S platform) #
• Workstation chipset for Xeon W #
• DMI: Gen 5 x4 (128 Gbps per direction) #
• PCIe (chipset): 12x Gen 5 + 12x Gen 4 #
• USB4 / TB4: 2x 40 Gbps from CPU #
• CPU OC: Not supported #
• Features: Intel vPro support #

Memory

LPDDR5M Memory

• Release Date: Unknown #
• Developed by Hynix #
• More power efficient than LPDDR5X #
• 0.98 V #

DDR6 System Memory

• Release Date: 2027 #
• Platform Validation: #
• Server Deployments: 2027 #
• Initial Draft from JEDEC: 2024 #
• Version 1.0 spec: mid-2025 #
• Four channels per module (2x that of DDR5, 4x that of DDR4) #
• Each channel is 24-bit (32-bit previously)
• 64 banks #
• Speeds starting at DDR6-8800 up to DDR6-17600 in 1st generation #
• LPDDR6 starts at LPDDR6-10667 with 24-bit channel with 2x 12-bit sub-channels #
• Maximum LPDDR6 data rate is expected to be LPDDR6-14400 #
• Commercial shipments now targeted for 2028 (delayed from 2027) #
• 4x24-bit sub-channel architecture (differs from DDR5's 2x32-bit) #
• CAMM2 form factor expected for high speeds #
• SK hynix, Samsung, and Micron actively designing in labs #

LPDDR6 Memory [updated]

• Release Date: H2 2026 #
• Samsung: 12 nm process, 10.7 Gbps, 21% improved energy efficiency #
• Hynix: 10 nm process (1c), 10.7 Gbps, 14.4 Gbps later #
• Hynix expects 20% improvement to efficiency
• Speeds are expected to reach up to 14 Gbps #
• Uses Dynamic Voltage and Frequency Scaling (DVFS) to dynamically adjust frequency and bandwidth
• JEDEC previews LPDDR6 roadmap: x6 sub-channel enables up to 512 GB densities #
• LPDDR6 SOCAMM2 module standard in active development #
• LPDDR6 Processing-in-Memory (PIM) standard nearing completion #
• SK hynix shipping world's first LPDDR6 on 1c nm (6th-gen 10 nm) process #
• SK hynix mass production in H2 2026: 16 Gb dies on 1c, up to 14.4 Gbps against LPDDR5X's 10.7 Gbps, and over 20% better efficiency #
• 1c is SK hynix's node for LPDDR6 alongside HBM4E and DDR5: 11-12 nm with 5-6 EUV layers, against 1b's 12-13 nm and 4 layers #
• CXMT is in high-volume manufacturing: 16 Gb dies at up to 12.8 Gbps in a package-on-package with about 1,295 balls. Xiaomi is first customer, in the Xiaomi 18 Fold # #
• Rambus announced a PMIC for LPDDR6 SOCAMM2 modules #

LPDDR6X Memory

• Release Date: 2027 #
• Qualcomm has received samples from Samsung as of Feb 2026 #

3D DRAM [added]

• Release Date: Unknown #
• Micron has dropped 4F2 DRAM, calling the density gain over 6F2 "a bit of a myth" because capacitor packing, not cell footprint, is the real limit #
• Micron keeps scaling 6F2 instead: 1-delta ramps in Boise in H2 2027, 1-epsilon after it moves to wafer bonding. 3D DRAM is a parallel path with no timeline #
• Samsung and SK hynix are both still developing 4F2; CXMT says its first 4F2 product is a server DDR5 RDIMM due by the end of 2026 #

YMTC LPDDR5X [added]

• Release Date: volume production starting at Fab 3 #
• About 5,000 wafers per month of 16 Gb LPDDR5X at 7,500 MT/s at Fab 2 #
• Moving to 9,600 MT/s using a vertical channel transistor 4F2 cell structure #
• Builds on Xtacking 4.0, separating memory cell wafers from peripheral logic and joining them by hybrid bonding, which positions YMTC well for 3D DRAM #

GDDR6W Graphics Memory

• Release Date: Unknown
• Builds on Samsung's Fan-Out Wafer-Level Packaging (FOWLP) technology
• Mounts the silicon memory dies on a wafer instead of a PCB
• Up to 22 Gbps per pin
• With a 512 bit interface that would be 1.4 TB/s
• Up to 24,000 MT/s
• Could be renamed GDDR6+
• Sources

  
  www.techpowerup.com/301573/samsung-develops-gddr6w-memory-standard-double-the-bandwidth-and-density-of-gddr6-through-packaging-innovations

HBM4 Memory [updated]

• Sampling Date: 2025 #
• As of Nov 2025: Samsung samples shipped #
• NVIDIA requests faster mass production #
• Mass production: 2026 # # #
• Samsung: Non-conductive film (NCF) assembly and hybrid copper bonding (HCB) #
• Micron shipped samples as of June 2025 #
• Micron: 12-Hi 36 GB, 2 TB/s #
• Micron in Sep 2025: 11 Gbit/s #
• Hynix tapeout in Q4 2024 #
• Hynix in March 2025: 12-layer HBM4 samples shipped with 36 GB capacity #
• Hynix in Sep 2025: 10 Gbps #
• 2048-bit interface #
• 6000 MT/s #
• Uses a copper layer as a conductor and oxide insulator instead of regular micro bumps #
• TSMC and Hynix have formed a joint venture to develop HBM4 #
• TSMC will use 12 nm and 5 nm to produce HBM4 #
• TSMC: 12-Hi (48 GB) and 16-Hi (64 GB) stacks #
• JEDEC published SPHBM4 (JESD330-4), enabling HBM4-class bandwidth on organic substrates using 512 signals with 4:1 serialization and the same DRAM dies as HBM4 #
• Expected to be used in AMD's MI450 #
• NVIDIA lowers HBM4 speeds for Vera Rubin VR200, because memory speeds not ready #
• Vera Rubin's HBM4 formally cut to 9.6 Gbps per pin #
• Micron reportedly no longer in the HBM4 race #
• Micron in high-volume HBM4 production (36 GB 12-hi, >11 Gb/s, >2.8 TB/s) #
• Samsung HBM4 in mass production: 11.7 Gbps, 1c DRAM + 4 nm logic base die #
• Samsung HBM4 mass-production for NVIDIA Vera Rubin confirmed, started February 2026 #
• Samsung warns 2027 memory shortage expected to be even wider than 2026 #
• Samsung 18-day worker strike starting May 21 will impact HBM production lines, ~3-4% of global DRAM at risk #
• SK hynix exploring Intel EMIB packaging as alternative to TSMC CoWoS #
• SK hynix is integrating HBM into CoWoS-L, CoWoS-S, CoWoS-R and Intel EMIB, and favours EMIB-T for its TSVs and vertical power delivery to 3D memory stacks #
• Intel EMIB-T enters volume production in 2027 with a reported 50% cost advantage over TSMC CoWoS; the TSV variant gives accelerators direct power connections, which multi-kilowatt single packages need #
• TSMC is answering with its own internally-named "EMIB-like" bridge packaging, developed with Kinsus Interconnect #
• TSMC is holding off on hybrid bonding for HBM and pushing 5 micrometer microbumps instead #
• SK hynix is reportedly behind Samsung on HBM hybrid bonding and has not sampled yet #
• Samsung Foundry gives roughly half of its SF4 4 nm capacity to HBM4 base dies, run on lines S5 and S6 at Pyeongtaek P2 and P3 #
• Samsung plans 50,000 HBM4 and HBM4E wafers per month in 2027, within roughly 250,000 total HBM wafers of which 80% would be HBM4/HBM4E #
• SK hynix began HBM4 shipments in Q3 2026 and expects HBM4 to pass HBM3E in both volume and revenue during Q4, ramping M15X to maximum capacity. 2027 HBM contracts are settled # #
• Samsung collaborating with AMD on HBM4 supply for Instinct MI455X GPUs #
• SK hynix and NVIDIA sign a multi-year partnership to co-develop memory for Vera Rubin, Vera CPUs, RTX Spark, and Jetson Thor #

HBM4E Memory [updated]

• Mass production: 2026 #
• SK Hynix development #
• Puts memory controller at the bottom of the memory stack #
• Samsung targets 13 Gbps / 3.25 TB/s, double the efficiency of HBM3e #
• Samsung redesigns power delivery to improve defect rate #
• Rambus IP is ready: up to 16 Gbps #
• Samsung plans 2 nm process for HBM4E base die #
• Samsung HBM4E previewed at GTC: 16 Gbps/pin, 4.0 TB/s, hybrid copper bonding for 16+ layers #
• TSMC plans 3 nm for custom HBM4E #
• Initial samples going out to customers in Q2 2026 #
• Samsung ships the industry's first 12-layer HBM4E samples: 14 Gbps (up to 16 Gbps), 3.6 TB/s per stack, 48 GB, built on 1c DRAM + 4 nm logic base die, with 16% better efficiency #
• SK hynix ships 12-layer HBM4E samples: 16 Gbps per pin, 48 GB per stack, over 20% better power efficiency and 17% more heat resistance than HBM4 #
• Samsung confirmed 16 Gbps per pin at Hot Chips 2026, for 4 TB/s per stack; it has shipped 14 Gbps parts since late May #
• Samsung HBM4E passed NVIDIA "Rubin Ultra" qualification at 14 Gbps per pin for 3.6-4 TB/s. Currently 12-high 48 GB, with 8-high 32 GB and 16-high 64 GB stacks to follow #
• SK hynix may dual-source HBM4E base dies from Intel Foundry alongside TSMC, and has named 1c as the DRAM process # #

HBM-PIM Memory

• Release Date: Unknown
• Stands for "processing-in-memory" #
• Adds computation functions to the memory stack #

HBM5 Memory [updated]

• Release Date: mass production around 2028 #
• Samsung's SEMICON Taiwan roadmap: 2x HBM4E performance, 20% better performance per watt, 20% lower thermal resistance, base die moving from 4 nm to Samsung's in-house 2 nm, and 12, 16 and 20-layer stack options #
• 20hi stack #
• Possibly using Hybrid Bonding Technology #
• Keeps 8 Gbps speed, but 4096 bit #
• Used by NVIDIA Feynman GPU #
• 400 to 500 GB of memory per package, 4,400 W of power #
• Intel: 16 compute dies and 24 HBM5 modules in a single package #
• SK hynix unveils its iHBM thermal solution (integrated cooling elements in the D2D PHY, 30% lower thermal resistance), slated for HBM5 #

HBM6 Memory

• Release Date: 2032 #
• 16 Gbps #
• 4096 bit #
• up to 20 layers, up to 120 GB per stack at 120 W #
• Immersion cooling and bumpless copper-copper bonding #

HBM7 Memory

• Release Date: 2035 #
• 24 Gbps #
• 8192 bit #
• 192 GB per stack at 160 W #

HBM8 Memory

• Release Date: 2038 #
• 32 Gbps #
• 16384 bit #
• 64 TB/s, 200-240 GB per stack at 180 W #

NVIDIA NVHBM Memory [added]

• Release Date: Unknown #
• Custom HBM that moves the memory controller off the compute die and into the 3D HBM stack's base die #
• Against standard HBM4E: up to 30% more bandwidth, 15% lower HBM power, up to 25% more usable compute die area #
• The custom PHY cuts I/O area by up to 67% versus JEDEC HBM4E, freeing up to 80% more usable silicon across the layout and simplifying interposer routing #
• Offered to third-party XPU customers through NVLink Fusion #
• NVIDIA requires the base die on TSMC 3 nm, so Samsung has to become a TSMC customer for the base die while supplying the DRAM itself #

Samsung zHBM Memory [added]

• Release Date: Unknown #
• Stacks memory directly on top of the processor rather than beside it, shortening the data path #
• Targets eight times the raw performance of current HBM #

Kepler Computing FeRAM Memory [added]

• Release Date: first HBM samples expected soon #
• HBM and SRAM alternative built on ferroelectric RAM with a new 3D stacking technique, aiming for standard HBM capacity at much lower cost #
• Needs no EUV: mature nodes only. With GlobalFoundries it converted a 28 nm fab into a memory fab in eight months against a typical 24-month lead time #
• About 2,000 wafers processed so far, after 35 composite iterations #

Intel HB3DM Memory

• Intel and SoftBank subsidiary Saimemory developing alternative to HBM #
• Z-Angle Memory (ZAM) technology: 9 layers (1 logic + 8 DRAM), hybrid bonding #
• ~5.3 TB/s per 10 GB module, over 2.5x HBM4 bandwidth #
• Limited by capacity (10 GB vs HBM4's 48 GB per stack) #
• Prototypes expected early 2028, commercial products 2029 #
• Presenting at VLSI 2026 in June #

Qualcomm HBC Memory [updated]

• Release Date: H1 2027 (Gen 1, with the AI250 accelerator) #
• First-generation HBC has passed silicon validation in Qualcomm's San Diego lab, with full read-write and near-memory computation working #
• The base die sits under the LPDDR stack so data travels microns instead of centimeters; LPDDR draws less power than the DDR in conventional HBM at similar bandwidth and capacity #
• High Bandwidth Compute: 3D-stacked LPDDR with through-silicon vias plus a near-memory compute die, positioned as an HBM alternative #
• Up to 133 TB/s on the AI250 card, with 6x the bandwidth per watt of HBM4 #
• That 133 TB/s is whole-accelerator bandwidth, not per module, and is 18x the LPDDR5X in the AI200 #
• Gen 2 sampling in 2028 with the Dragonfly AI300 #

Game Consoles

Sony PlayStation 6 [updated]

• Release Date: Unknown #
• Production: Q2 2027 #
• Could launch along a new portable gaming handheld #
• Less processing power than new Xbox #
• Codename: PS6 Orion #
• 2.5-3x raster perf of PS5, and 6-12x RT performance #
• 4K 120 FPS in most games #
• AMD RDNA 5 GPU with 52-54 CUs at 2.0-3.6 GHz #
• 34-40 TFLOPs of theoretical performance #
• Up to 30 GB GDDR7 memory #
• GDDR7 on a 160-bit bus supporting up to 40 GB, with 30 GB the more likely configuration #
• Both PS6 and Xbox Helix silicon have taped out, rated at 40 TFLOPS and 56 TFLOPS respectively, though TFLOPS should not be normalized across architectures #
• Analysts predict PS6 could cost up to $999 for top variant #
• Base model estimated ~$600 digital, ~$750 disc #
• Leaker claims PS6 won't be delayed, AMD actively validating Canis and Orion APUs #
• Sony confirms frame generation coming to PlayStation "at some point" #
• Sony patent US 2026/0320740 A1 "Generation Super Sampling" describes predicting the next frame forward from a single rendered frame using motion vectors and recent controller input, with a non-AI block-shift fallback #
• Upgraded PSSR uses INT8 FSR 4 implementation #
• Sony CEO Hiroki Totoki confirms price and launch date not yet decided due to DRAM pricing uncertainty #
• Totoki repeated to the Wall Street Journal that Sony "has not yet decided" on timing or price, citing memory prices expected to stay high through FY2027 #
• RAM and NAND alone are estimated at over $680 #
• Sony's bill of materials is put roughly $200 under Xbox Helix, implying about $1,000-1,100 if Sony prices aggressively #
• Sony stopped shipping its last standalone 4K Blu-ray player in Japan in October, leaving the PS5 as its only 4K disc player there, and has not said whether the PS6 will have a drive #
• Sony signaled $900+ pricing ("we don't intend to sell hardware at significant losses"); the BOM is estimated at ~$960, with launch slated for 2028 # #
• Portable PS6 also in development; developers already optimizing for its APU before dev kits ship #
• A $600 PS6 Portable is "definitely not possible right now" because of LPDDR pricing #
• May be the only portable console with an RDNA 5 iGPU - an "exclusivity of sorts" rather than a contract, since AMD reportedly wants a commitment of around 10 million units before it engineers custom silicon. That is also given as the reason Xbox cancelled its in-house handheld #
• PS6 Portable's "Canis" APU reportedly pairs four Zen 6c cores with two Zen 6 LP cores — corroborated by a new AMD Linux kernel patch adding an x86 low-power core type #

Microsoft Xbox "Project Helix" [updated]

• Release Date: holiday 2028 for the console, with a next-gen handheld in holiday 2027 #
• Codename: Project Helix #
• New Xbox CEO Asha Sharma confirmed next-gen hardware is coming #
• Rumored to be a hybrid console/PC device #
• Reportedly plays both Xbox and PC games #
• Sharma states Project Helix will "lead in performance" #
• May be a response to Steam Deck/Steam Machine rise #
• More info possibly revealed at GDC (March 9-13) #
• AI integration expected but Sharma claims she "will not tolerate AI slop" #
• Speculation and skepticism surround Sharma's leadership direction #
• Dev kits shipping end of 2027, confirming 2027-2028 launch window #
• AMD SoC with FSR Diamond, RDNA 5 / UDNA graphics IP #
• Designed to play Xbox console and PC games #
• Backwards compatible with Xbox Series, Xbox One, and Xbox 360 games #
• Analysts predict pricing as high as $999 #
• Internally projected at $1,200 to $1,800 unless Microsoft subsidizes it; the current Series X with a drive sells for $799.99 #
• Helix SoC taped out at about 56 TFLOPS, roughly 40% over the PS6's 40 TFLOPS on paper #
• "FSR Diamond" is the Helix-era upscaler, teased with machine-learning upscaling and multi-frame generation; FSR 4.1 is the stopgap now reaching Xbox Series X|S # #
• Will use off-the-shelf AMD APU with RDNA 5 and Zen 6/6c cores, no custom silicon #
• Leaker claims 68 RDNA 5 CUs, 48 GB GDDR7, chiplet design, equivalent to $2-3,000 gaming PC #
• Xbox VP confirms 1st-party Xbox console, leaves door open for 3rd-party variants #
• Now described as a "family of devices" rather than one console; CEO Asha Sharma told staff it will be "a great console first" with portable play in the same lineup # #
• No disc drive expected; "Positron" disc-to-digital entitlement program planned #
• Disc-to-digital attestation has launched for most Xbox One and Series X disc games and exited testing, which reads as groundwork for a drive-less Helix # #
• Not settled, though: Microsoft is still surveying Xbox Insiders on whether disc installs are "Not Necessary", "Nice to Have" or a "Must Have", and has posted an "Xbox Games Supply Strategist" role covering physical games # #
• Xbox Game Dev Update event featured Helix preview #

Valve Steam Deck 2 [updated]

• Release Date: 2028 #
• Uses off-the-shelf AMD APU instead of semi-custom #
• Likely Zen 6 cores with RDNA 5 GPU IP #
• DRAM / NAND shortages could cause delays #
• Valve developer confirms Steam Deck 2 still in active development #
• Valve reiterated a Steam Deck 2 only if it delivers a generational leap; efficiency remains the blocker, with a launch not expected before ~2028 # #
• Valve says the DRAM shortage has not changed its plans or goals for the next handheld, only the timing #
• New AMD codename "Gainsborough" appeared in Adrenalin 26.9.2 - Aerith's surname, matching Valve's Final Fantasy VII naming - on an FF6 BGA package with 1,179 contacts, reportedly on TSMC N3P with Zen 6 and RDNA 5 #
• A Gainsborough engineering sample on OpenBenchmarking shows 6 cores / 12 threads at a 2.4 GHz base, 50% more cores than the current Deck, with 24 GB of LPDDR5 at 9,600 MT/s #
• Caution: the same FF6 package has also been tied to AMD's Ryzen Z3 handheld chips, so the customer is not confirmed #
• An off-the-shelf part rather than custom silicon is expected, which would leave the Deck 2 on RDNA 3.5 while Sony's handheld takes RDNA 5 #

Nintendo Switch 2 Updates [updated]

• Release Date: Launched 2025
• Production cut by 33% (6 M to 4 M units) due to softening US sales and memory costs #
• EU revision planned with user-replaceable battery for right-to-repair compliance #
• $50 price increase to $499 (US) / €499 (EU) on September 1, 2026 due to rising DRAM and BOM costs #
• Sales target lowered to 16.5 million units for FY2027 (down 16.9%) #
• Nintendo is evaluating a Switch 2 OLED using a Samsung rigid OLED panel; if greenlit, mass production would start end-2027 for an early-2028 launch #
• The European "V2" revision keeps the same Innolux LCD rather than the hoped-for Sharp panel, but drops the battery adhesive to meet EU battery rules taking effect in mid-February 2027; the motherboard was reworked #
• Samsung presents 8LPU+ at IEDM 2026 on December 14: 12% more performance, 15% less power, 8% smaller area than 8LPU, DUV-only. Floated as the node for a cheaper Switch 2 Lite, since the Switch 2's T239 is built on Samsung 8 nm. Nothing announced #
• Nintendo says physical Switch 2 games are here to stay #

Silicon Fabrication Tech

TSMC 2 nanometer [updated]

• Release Date: Q4-2024 Risk Production #
• Trial run in Q1 2025: very successful #
• Volume production: Q4 2025 # #
• Mar 2026: All capacity almost sold out until 2027 #
• June 2020: TSMC is accelerating R&D
• Sep 2020: fab construction has begun
• Capacity end of 2025: up to 80,000 wafers per month #
• 2026: 125,000 wafers per month #
• Aug 2025: In 2026, two plants expected with 60,000 wafers per month #
• Oct 2025: First wafers produced at Fab 22 #
• N2 entered high-volume manufacturing in June 2026 and now accounts for ~3% of wafer revenue, with a steep ramp expected in Q3 2026 and 4x the tape-outs of N3 at the same stage # #
• Will use Gate-All-Around (GAA) technology
• Probable VVIP customer: Apple #
• 15+ customers secured #
• First batch fully reserved for Apple #
• Yield rate: 90% #
• Other customers: NVIDIA, AMD and Broadcom #
• Confirmed customers include AMD EPYC "Venice" and Apple's A20 (iPhone 18 Pro) and M6 #
• "Unprecedented Demand" #
• Multi-bridge channel field effect transistor (MBCFET) architecture
• 10-15% speed improvement over N3 at same power, or 25-30% power at same speed
• GAAFET nanosheets deliver up to 15% more performance or 30% less power and 15% higher density; N2P follows in H2 2026, N2X in 2027, and N2U in 2028 #
• Several process variants: N2, N2P and N2X
• Not using High-NA EUV #
• Nanosheet transistors
• AMD EPYC "Venice" is the first HPC product to enter production on N2, ramping high-volume as of May 2026 #
• N2 output target raised to 120,000 wafers per month by the end of 2026 # #
• Wafer prices rise 3% to 6% from January 2027, with 2 nm and 3 nm taking the steepest increases #
• CoWoS-L is in mass production at 5.5x the reticle limit (858 mm2 of logic in 4,720 mm2 of silicon) at about 98% yield, with 9.5x planned for 2027 and 14x for 2028-2029 #
• CoWoS prices may rise up to 20% as demand spreads from AI GPUs to server CPUs and custom ASICs; tool lead times now reach eight months #

TSMC 1.6 nanometer [updated]

• Release Date: 2027 or early 2028 #
• Backside power delivery #
• Will be used by NVIDIA Feynman GPUs #
• NVIDIA has secured A16 for "Feynman", skipping the N2 family entirely; mass production H2 2028, with backside power delivery, SoIC 3D chiplet stacking and CoWoS-L or panel-level packaging #

TSMC 1.4 nanometer [updated]

• Risk Trial Production: 2027 #
• Pilot Runs: 2027 #
• Mass Production: H2 2028 # #
• Ahead of schedule as of Apr 2025 #
• Fab construction begins as of Nov 2025 #
• Codename "A14" #
• Not using High-NA EUV # #
• Uses 0.33-NA EUV #
• 15% speed improvement at same power #
• 30% power reduction at the same speed #
• 20% increase in density #
• $49 billion single-site investment #
• Taichung Phase 2 site ahead of schedule; trial production possibly as early as Q3 2027 #
• Mass production now expected H2 2028 #
• Pilot production under way at Baoshan Fab 20 and Fab 25, risk production in 2027, high-volume manufacturing in 2028 in Taiwan. The schedule may be pulled in by a few months if yields hold # #
• The Taichung Phase II fab is due for completion by April 2027, aided by AI inspection and VR training #
• Ends eight years of SRAM scaling stagnation: the 6T bitcell drops from about 0.021 to 0.017 micrometer2, a 19% shrink #
• ASML and TSMC move High-NA EUV from 6-inch to 12-inch photomasks, removing stitching constraints and raising scanner productivity #

TSMC 1.3 nanometer

• Codename "A13" #
• Direct shrink of A14, 6% area savings, fully backward compatible with A14 designs #
• Production scheduled for 2029 #

TSMC 1.2 nanometer

• Codename "A12" #
• A14 platform enhancement with Super Power Rail backside power delivery for AI and HPC #
• Production scheduled for 2029 #
• N2U (2 nm enhancement): 3-4% speed gain or 8-10% power reduction from N2P, production 2028 #
• 14-reticle CoWoS (10 compute dies + 20 HBM stacks) slated for 2028, beyond 14 reticles in 2029 #

TSMC 1 nanometer

• Release Date: around 2030 #
• Fab construction: 2026 #
• Uses Semi-metal bismuth for contact electrodes #
• Chip plan planning has started as of Nov 2022 #
• Codename "A10" #
• Uses High-NA EUV #

Samsung 3 nanometer

• Mass Production: H1 2022
• "Initial production" started as of Jun 30th 2022
• Uses Gate All Around FET transistors (GAA), Multi-Bridge-Channel FET (MBCFET)
• 45% less power while delivering 23% more performance
• 35% less silicon space taken per transistor (vs. 7 nm)
• 16% less silicon space taken per transistor (vs. 5 nm)
• 2nd generation 3 nm expected in 2025, reduces power by 50%, improves perf by 30%, reduces area by 35%
• Samsung claims 60-70% yields as of May 2023 #
• In Jul 2023 Samsung claimed 60% yields, and points out that this is better than TSMC #
• According to a newer report, both Samsung and TSMC are struggling with yields for their 3 nm node #
• Trial run of second-generation 3 nm process starting in early 2024 #
• Sources

  
  www.techpowerup.com/296345/samsung-begins-chip-production-using-3nm-process-technology-with-gaa-architecture
  www.techpowerup.com/287565/samsung-foundry-announces-gaa-ready-3nm-in-2022-2nm-in-2025-other-speciality-nodes
  www.techpowerup.com/283983/samsung-3-nm-gaafet-node-delayed-to-2024
  www.techpowerup.com/266368/samsung-to-commence-5nm-euv-mass-production-in-q2-2020-develop-3nm-gaafet-node
  www.techpowerup.com/265751/samsung-to-deliver-3-nm-manufacturing-process-in-2022-with-next-generation-transistors
  

Samsung 2 nanometer [updated]

• Mass production: Q4 2025 #
• Uses Multi-Bridge-Channel FET (MBCFETTM)
• Feb 2024: order received for AI chips #
• Possibly using backside power delivery #
• Efficiency improved by 25%, performance by 12%, area by 5% #
• Samsung's new Texas fab might be 2 nm #
• Capacity in S3 foundry: 7000 wafers per month #
• First product: Exynos 2600 flagship SoC #
• Tesla's AI5 SoC will be mass-produced at Samsung's Taylor, Texas fab on the SF2 (2 nm) node #
• Test run got 40%+ yields #
• Anthropic's Broadcom-designed AI ASIC is slated for Samsung SF2: about 4,000 INT8 TOPS, 1,300 W per chip, 192 to 288 GB of HBM3E, initial volume around 200,000 chips #
• Samsung Foundry is preparing price increases after a demand spike #
• Groundbreaking on a second Taylor, Texas fab in November, targeting production in 2030 #
• Samsung and Qualcomm have formed a 2.1D packaging alliance that replaces silicon interposers with organic bridges built from PCB-style epoxy and copper redistribution layers #
• Sources

  
  www.techpowerup.com/287565/samsung-foundry-announces-gaa-ready-3nm-in-2022-2nm-in-2025-other-speciality-nodes
  

Samsung 1.4 nanometer

• In planning as of Oct 2022
• Plant construction: Q2 2025 #
• Mass Production: 2027 or 2028 #
• Mass production pushed from 2028 to 2029; the first Samsung node to use High-NA EUV, with about seven ASML tools due by end-2027 #
• Could be canceled as of Mar 2025 #
• GAA (gate-all-around)
• 2.5D/3D integration
• Micro-bumps
• Sources

  
  www.techpowerup.com/299538/samsung-electronics-unveils-plans-for-1-4-nm-process-technology
  

Samsung 1 nanometer [updated]

• Mass Production: 2029 #
• Samsung will try to match or beat TSMC with 1 nm time to market #
• High-NA EUV adoption deferred to this node in 2030, which would make Samsung the last of the three leading-edge foundries to adopt it; TSMC is expected in 2029, Intel is already running it on 18A and 14A #

Intel 18A-P [updated]

• Release Date: risk production started 2026 #
• Enhanced version of 18A: about 9% more performance at the same power, or 18% less power at the same performance #
• First product is the Xeon 7 "Diamond Rapids" #
• 18A yield issues resolved, running ~30,000 wafers per month; external roadmap focuses on 18A-P, 18A-PT, and 14A #
• Nova Lake is the first 18A-P client product, confirmed by CEO Lip-Bu Tan and tracking ahead of schedule #
• Socionext will use 18A-P for custom SoCs, starting with a high-performance compute chiplet #
• Cadence has certified AI-driven reference flows for both 18A-P and 14A #
• Intel Foundry has run one million High-NA EUV wafers; High-NA is in use on 18A #
• Intel's New Mexico site handles multi-chiplet assembly using EMIB, EMIB-T and Foveros; EMIB-T reaches volume production in 2027 # #
• Some 18A capacity in Oregon is being converted to Intel 3 to feed Xeon demand, with the added Intel 3 capacity in production in H2 2027 #

Intel 14A [updated]

• Release Date: 2027 #
• "Engaging with multiple customers" #
• "Off to a great start" #
• 14 Angstrom = 1.4 nanometer #
• 15% performance per watt over Intel 18A #
• 20% increase in transistor density #
• High-NA extreme ultraviolet (EUV) # #
• Also 14A-E process with additional 5% performance boost #
• 15-20% performance per watt over 18A #
• Uses ASML TWINSCAN EXE:5200B #
• Uses "Turbo Cells" to boost frequency and cut power #
• NVIDIA and AMD exploring use of 14A #
• Intel Foundry nears major customer wins: Apple, AMD, Google, NVIDIA weighing deals #
• 14A PDK v1.0 release is key catalyst for new contracts #
• Intel EMIB demonstrated 47 tiles in a single package #
• Tesla signed as first major 14A customer for Terafab AI chip complex #
• Apple to use Intel 14A for A21 iPhone SoCs, expected ~2028 #
• PDK at v0.5; customers awaiting v0.9 for design finalization #
• First node to use ASML High-NA EUV #
• Intel said 18A yield issues are resolved and external efforts now center on 18A-P and 14A #
• Risk production for internal products in H2 2027, full high-volume ramp in 2028, per CEO Lip-Bu Tan #
• Intel Foundry's Naga Chandrasekaran expects 14A within 5% of TSMC's A14; tens of thousands of 14A wafers have already run in pilot production #
• The 0.9 process design kit was released in late October, called the "holy grail" by CEO Lip-Bu Tan because customers can start trial designs that carry over to production. PDK 1.0 follows in Q1 2027 # #
• Against 18A: 15-20% more performance at the same power, or 25-35% less power at the same performance, with up to 30% higher density #
• 14A capacity is put at about 6,000 wafers per month by the end of 2027, rising to 24,000 in 2028 #
• Fab 62 at the Ocotillo campus in Chandler, Arizona has begun equipment installation, operations expected by the end of 2028; it could support 18A, 18A-P and 14A #
• Intel has broken ground on a photomask facility in Santa Clara and installed the first structural truss at New Albany, Ohio #
• CEO Lip-Bu Tan has spoken with AMD CEO Lisa Su about possible areas of cooperation without naming them; AMD is reported to be evaluating 14A #

Intel 10A

• Release Date: end of 2027 #
• 10 Angstrom = 1 nanometer #

Intel 7A

• Release Date: Unknown
• Added to Intel's foundry roadmap alongside 10A, following 14A #
• 7 Angstrom = 0.7 nanometer

SMIC 5 nanometer

• Release Date: 2025 #
• Difficult due to lack of readily available EUV equipment in China #
• 40-50% more expensive than TSMC #

Rapidus 2 nanometer [updated]

• Release Date: 2027 #
• New fab project based out of Japan #
• $1.7B received in Mar 2026 #
• Uses ASML EUV #
• Goal: 25,000 wafers per month #
• Could use glass panel packaging #
• Packaging roadmap to about 2030: interposers from four reticles (3,320 mm2) through six (4,980 mm2) to eight (6,640 mm2), on 600 x 600 mm panels. An eight-reticle interposer yields 4 units on a 300 mm wafer against 49 on a 600 x 600 mm panel #
• "Rapidus CORE" announced as a global framework for development and mass production #

Rapidus 1.4 nanometer

• Release Date: Unknown #
• Plant construction in 2027 #

Elon Musk "Terafab" [updated]

• Release Date: Years from completion #
• $20 billion semiconductor manufacturing plant (Tesla / SpaceX / xAI joint venture) #
• Location: Austin, Texas #
• Intel Foundry joins project, providing silicon design and advanced packaging (EMIB) #
• Two chip families: efficient inference and space-hardened chips #
• Years from completion #
• First phase cost: $55 billion, could reach $119 billion total #
• TSMC is in talks about a Terafab joint venture, confirmed by Elon Musk #
• Intel CEO Lip-Bu Tan confirms Intel stays in, with Intel IP as Terafab's base; TSMC would not operate capacity itself #
• The "Terafab" name is in a trademark dispute #

GlobalFoundries FDX Fusion [added]

• Release Date: mass production at Dresden in 2028 #
• A 7 nm-class process built on fully-depleted silicon-on-insulator rather than FinFET or GAA #
• Two new 300 mm fabs planned at Malta, New York under a U.S.-Japan initiative worth up to $21 billion; about $10 billion each, groundbreaking late 2026, production from 2029, around 900,000 wafers a year per fab, baseline capacity around 2031-2032 and 2033 #
• A separate five-year, $2 billion deal brings CoWoS silicon interposers to New York, ramping to volume in H1 2028 - the first real second source for TSMC's packaging bottleneck #
• Co-packaged optics for AMD's Instinct MI500 accelerators are slated for 2027; $955 million of GF's CHIPS award is reallocated to silicon photonics, SiGe and advanced packaging at Malta and Burlington # #

Chinese Domestic Lithography [added]

• Shanghai Yuliangsheng Technology has begun limited production of immersion DUV scanners: five systems this year and about 20 by 2027, with first deliveries to SMIC, CXMT and Hua Hong #
• Startup Langdao Silex demonstrated the first homegrown EUV laser source, the FlintNano LPP-OXXO: over 15 W of EUV output, a 1,000 W driving laser at 1-20 kHz, over 2% conversion efficiency, over 100 hours of continuous operation, roughly 90% domestic components #
• The prototype is said to be usable for wafer exposure testing, though it still needs tuning #

Nanya Fab5A EUV DRAM [added]

• Release Date: wafer starts in H2 2027 #
• Up to NT$346.6 billion (about $10.7 billion) committed through 2026-2029, covering 10 nm-class 1b through 1e nodes and introducing EUV lithography; total build-out estimated at roughly $16 billion #
• Capacity roadmap: 30,000 wafers per month in 2028, 35,900 in 2029, planned maximum around 45,000 #
• 1c pilot production has begun; 1d is in development #

IBM 0.7 nanometer

• Release Date: roughly five years out (research) #
• World's first sub-1 nm (7 angstrom) node, using a 3D vertical-transport "nanostack" nanosheet architecture #
• About 100 billion transistors on a fingernail-size die, with up to 50% more performance or 70% better efficiency than 2 nm #
• Uses ASML High-NA EUV; unveiled at VLSI 2026 #

Other

Hynix HBF High-Bandwidth Flash [updated]

• Release Date: Unknown #
• New memory architecture that comes 3D NAND storage with HBM-like bandwidth #
• 16 BiCS8 dies stacked #
• 4 TB memory usable like VRAM #
• pSLC #
• Hynix and Sandisk working on standardization #
• Sandisk and SK hynix published the first HBF technical specification through the Open Compute Project; Google and Tenstorrent joined the consortium during standardization #
• SK hynix confirmed in its Q3 2026 results that HBF work continues #
• Micron is exploring a rival idea, "near-GPU NAND": lower-density flash on the GPU package or PCB, trading density for I/O speed and read latency to sit between HBM and system storage #

NVIDIA SOCAMM Memory

• Release Date: Unknown #
• Developed by NVIDIA #
• System On Chip Advanced Memory Module—SOCAMM #
• Adapts CAMM for higher memory density #
• 694 I/O pins vs 644 on LPCAMM and 260 on DRAM #
• LPDDR5X substrate integration #
• Partners: SK Hynix, Samsung, Micron #
• Micron 192 GB SOCAMM2 modules in high-volume production for Vera Rubin NVL72 #
• SK hynix 192 GB SOCAMM2 now in mass production on 1c nm (6th-gen 10 nm) LPDDR5X #
• Rambus unveiled first commercial SOCAMM2 server module chipset #

ASRock HUDIMM Memory

• Release Date: 2026 #
• DDR5 with single 40-bit sub-channel (half bandwidth and density at rated speeds) #
• Targets entry-level builds during DDR5 shortage #
• Can pair with regular UDIMMs for asymmetric configs #
• Also developed HSODIMM (half SO-DIMM) variant #
• Partnered with Team Group for manufacturing #
• Gigabyte rolled out BIOS support across all Intel 800/700/600 series motherboards #
• Supports mixed HUDIMM + standard UDIMM configurations (e.g. 8 GB HUDIMM + 16 GB UDIMM = 24 GB with 3 sub-channels) #

Toshiba/WD 5-Bit-per-Cell NAND Flash (PLC)

• Release Date: Delayed to 2025
• Stores an additional bit of information per cell (compared to QLC)
• 32 states per cell
• Will enable even cheaper SSDs, probably at a performance cost
• Sources

  
  www.techpowerup.com/283337/western-digital-may-introduce-penta-layer-cell-plc-nand-by-2025
  www.techpowerup.com/258650/toshiba-talks-about-5-bit-per-cell-plc-flash-memory
  

Samsung Z-NAND

• Release Date: Unknown #
• Up to 15x performance of regular NAND and ~80% lower power use #
• Direct GPU/accelerator access #
• Could make persistent storage behave like fast memory #
• Competitor to Kioxia's XL-FLASH #

Toshiba XL-Flash [updated]

• Kioxia is pitching XL-FLASH as memory rather than storage with the XL1 series, a CXL memory expansion module; evaluation samples went to ecosystem partners in August 2026 #
• The GP1 series PCIe 6.0 NVMe SSD uses XL-FLASH generation 2 for up to 10 million random read IOPS with GPU direct access, extending HBM with a flash tier at far lower cost. Evaluation samples by the end of 2026 #
• Developed by Toshiba
• Uses existing SLC flash technology to improve latencies
• 1/10th the read latency of TLC
• Good for random IOPS and better QoS at shallow queue depth
• Can combine SLC and TLC/QLC for tiered, cost-optimized storage
• Intel Optane memory competitor
• 128 gigabit (Gb) die (in a 2-die, 4-die, 8-die package)
• 4 KB page size for more efficient operating system reads and writes
• 16-plane architecture for more efficient parallelism
• Fast page read and program times
• Sources

  
  www.techpowerup.com/257904/toshiba-memory-introduces-xl-flash-storage-class-memory-solution
  www.techpowerup.com/246611/toshiba-looks-to-take-on-optane-with-xl-flash-low-latency-3d-nand-technology
  

Hynix 321-layer 3D NAND Flash

• Release Date: H1 2025 #
• Mass Production: August 2025 #
• Transfer rate increased from 164 MB/s to 194 MB/s #
• 1 Tb capacity with TLC #
• 20 Gbit/mm² #
• 41% more bit growth, 13% shorter read latency, 12% faster program performance, 10% better read power efficiency #
• 16 KB page size, 4 planes #
• QLC: 6 planes #
• QLC: Write performance improved by 56%, read performance improved by 18%, 23% better power #
• 2400 MT/s #
• Made from three stack of 107-layers each #
• QLC cSSDs now shipping, Dell first customer #

Hynix 400-layer 3D NAND Flash

• Release Date: 2025 Q4 #
• Uses Hybrid Bonding Technology #

Micron G11 400-layer 3D NAND Flash [added]

• Release Date: H2 2027 #
• Micron's first 3D-stacked NAND, using wafer-to-wafer bonding to roughly double capacity over the shipping G9 generation #
• Density 42 Gb/mm2 against G9's 21, I/O 5,400 MT/s against 3,600, with about 25% lower energy per bit #
• Splits each wafer into a memory cell wafer and a peripheral logic wafer joined by hybrid bonding, following YMTC's Xtacking approach #

Samsung 290 layer 3D NAND Flash

• Release Date: 2024 #
• Mass Production started of 1 Tbit TLC: Apr 2024 #
• 9th generation V-NAND #
• 11 nm class process #

Samsung 280-layer 3D NAND QLC Flash

• Release Date: H1 2026 #
• Density: 1 Tbit #
• Density: 28.5 Gb/mm² at 3.2 GB/s #

Samsung 430-layer 3D NAND Flash

• Release Date: 2026 #
• Uses Bonding Vertical Technology, so separate layers can be bonded together, to improve yields #
• Up to 60% density improvement #

Kioxia 1000-layer 3D NAND Flash

• Release Date: 2027 #
• QLC and PLC #

Samsung 1000-layer 3D NAND Flash

• Release Date: 2030 #
• Multi-BV NAND design #
• Stacks four wafers to overcome structural limits #
• Samsung demonstrated 900-layer V-NAND by bonding two 450-layer chips via Cell Multi-Bonding (CMB); high-volume production a few quarters out #

Kioxia / Sandisk BiCS10 332-layer 3D NAND Flash [updated]

• Release Date: sampling 2026 # #
• 10th-generation BiCS FLASH: 332 layers, roughly 59% higher bit density than BiCS8 #
• 4.8 Gb/s interface (+33%), CBA wafer bonding, and 18-34% better I/O power efficiency #
• Initially 1 Tb TLC, targeting enterprise and data-center SSDs #
• Kioxia's first PCIe 6.0 enterprise SSD, the CM10 Series, uses BiCS 10 TLC: up to about 92% higher sequential read and 85% higher random read than the previous generation, with direct cold-plate liquid cooling and NVIDIA CMX support #
• The QLC variant passes 37 Gb/mm2, a 60% bit density increase over the 8th generation, and is the first QLC 3D flash to reach a 4.8 Gb/s interface #
• 9th-generation BiCS 1 Tb TLC sample shipments also began #

YMTC 294-layer 3D NAND Flash

• Shipping as of Jan 2025 #
• TLC #
• 232 active layers #
• Uses hybrid bonding #
• XTacking 4.0 #
• First SSD using the flash is from Zhitai #
• YMTC NAND now ships in German Lenovo ThinkBook laptops — the first YMTC flash in a laptop sold outside China #

UFS 5.0 [updated]

• Release Date: mass production Q4 2026 #
• Industry-first UFS 5.0: up to 10.8 GB/s read and 9.5 GB/s write (about 2x UFS 4.1), with 40% better power efficiency #
• JEDEC standard, up to 1 TB capacity #
• Kioxia also announced UFS 5.0: MIPI M-PHY v6.0 and UniPro v3.0 with HS-Gear6, up to 46.6 Gb/s per lane and about 10.8 GB/s effective dual-lane. Samples in 512 GB and 1 TB, mass production by the end of 2026 #

Seagate 50 TB HAMR Hard Drives [added]

• Release Date: customer validation in 2027 #
• Built on Mozaic 5+, exceeding 5 TB per platter; ten platters gets to 50 TB #
• The current Mozaic 4+ platform tops out at 44 TB and should account for 50% of Seagate's HAMR exabytes by the end of 2026 #

PCI Express 6.0

• Release Date: 2023
• Hardware expected: 2024
• Spec version 1.0 published as of Jan 2022
• Spec version 0.9 published as of Oct 2021
• Spec version 0.5 published as of Feb 2020
• Spec version 0.7 published as of Nov 2020
• 64 GT/s raw bit rate, up to 256 GB/s with x16
• Rambus has controller IP ready as of Jan 2022
• Rambus has PHY and controller ready as of Oct 2022
• Includes low-latency Forward Error Correction (FEC) with additional mechanisms to improve bandwidth efficiency
• Maintains backwards compatibility with all previous generations of PCIe technology
• New physical layer with PAM4 (pulse amplitude modulation) signaling replacing NRZ (non-return to zero)
• Sources

  
  www.techpowerup.com/300225/rambus-delivers-pcie-6-0-interface-subsystem-for-high-performance-data-center-and-ai-socs
  www.techpowerup.com/291356/rambus-delivers-pcie-6-0-controller-for-next-generation-data-centers
  www.techpowerup.com/290805/pci-sig-releases-pcie-6-0-specification-64-gt-s-per-lane
  www.techpowerup.com/287573/pci-sig-announces-pcie-6-0-final-draft-specification
  www.techpowerup.com/274253/pcie-6-0-specification-reaches-milestone-remains-on-track-for-a-2021-release
  www.techpowerup.com/264172/pci-express-gen-6-reaches-development-milestone-on-track-for-2021-rollout
  www.techpowerup.com/260177/pci-express-gen-6-0-specification-to-finalize-by-2021
  www.techpowerup.com/256634/pci-sig-announces-pcie-6-0-specification
  

PCI Express 7.0

• Release Date: 2025 #
• Version 0.3 released as of Jun 2023 #
• Version 0.5 released as of Apr 2024 #
• Version 0.7 released as of Jan 2025 #
• Version 0.9 released as of Mar 2025 #
• Version 1.0 released as of Jun 2025 #
• Spec is work in process as of 2022
• 128 GT/s raw bit rate, up to 512 GB/s with x16 #
• PAM4 signaling #
• Improved power efficiency #
• Backwards compatible with all previous versions of PCIe #

PCI Express 8.0

• Release Date: 2028 #
• Version 0.3 released as of Sep 2025 #
• 256 GT/s #
• Continues to use PAM4 signaling #
• Backwards compatible #
• Draft v0.5 released #
• Evaluating new connector technology; current copper connector may be a limiting factor at 256 GT/s #
• Targets 1 TB/s bidirectional bandwidth in x16 configuration #